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48SD1616 데이터시트 PDF




Maxwell Technologies에서 제조한 전자 부품 48SD1616은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 48SD1616 자료 제공

부품번호 48SD1616 기능
기능 256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks
제조업체 Maxwell Technologies
로고 Maxwell Technologies 로고


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48SD1616 데이터시트, 핀배열, 회로
48SD1616
256 Mb SDRAMwww.DataSheet4U.com
4-Meg X 16-Bit X 4-Banks
Logic Diagram (One Amplifier)
FEATURES:
• 256 Megabit ( 4-Meg X 16-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space
radiation
• Total Dose Hardness:
>100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
SELTH > 85 MeV/mg/cm2 @ 25°C
• JEDEC Standard 3.3V Power Supply
• Operating Current: 115 mA
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125 °C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations
Sequential (BL =1/2/4/8)
Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 72-Pin RAD-PAK® Flat Package
DESCRIPTION:
Maxwell Technologies’ Synchronous Dynamic Random
Access Memory (SDRAM) is ideally suited for space
applications requiring high performance computing and
high density memory storage. As microprocessors
increase in speed and demand for higher density mem-
ory escalates, SDRAM has proven to be the ultimate
solution by providing bit-counts up to 256 Mega Bits and
speeds up to 100 Megahertz. SDRAMs represent a sig-
nificant advantage in memory technology over traditional
DRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation,
the ability to interleave between banks masking pre-
charge time.
Maxwell Technologies’ patented RAD-PAK® packaging
technology incorporates radiation shielding in the micro-
circuit package. It eliminates the need for box shielding
for a lifetime in orbit or space mission. In a typical GEO
orbit, RAD-PAK® provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with
screening up to Maxwell Technologies self-defined Class
K.
01.07.05 REV 4
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice 1
©2005 Maxwell Technologies
All rights reserved.




48SD1616 pdf, 반도체, 판매, 대치품
256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
48SD1616
www.DataSheet4U.com
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(VCC= 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS MIN
MAX UNITS
Standby Current in Power Down
( input signal stable)5
ICC2PS
CKE = VIL
tCK = 0
1, 2, 3
2 mA
Standby Current in non power down6
Standby Current in non power down
( Input signal stable)7
Active standby current in power
down1,2,4
Active standby current in power down
(input signal stable)2,5
Active standby power in non power
down1,2,6
Active standby current in non power
down ( input signal stable)2,7
Burst Operating Current1,2,8
CAS Latency = 2
CAS Latency = 3
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
CKE, CS = VIH
tCK = 12 ns
CKE = VIH
tCK = 0
CKE = VIL
tCK = 12 ns
CKE = VIL
tCK = 0
CKE, CS = VIN
tCK = 12 ns
CKE = VIH
tCK = 0
tCK = min
BL = 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
20 mA
9 mA
4 mA
3 mA
30 mA
15 mA
mA
110
145
Refresh Current3
ICC5 tRC = min 1, 2, 3
220 mA
Self Refresh current9
ICC6 VIH>VCC - 0.2V 1, 2, 3
VIL < 0.2 V
3 mA
Input Leakage Current
ILI
0<VIN<VCC
1, 2, 3
-1
1
uA
Output Leakage Current
ILO
0<VOUT<VCC
1, 2, 3 -1.5 1.5 uA
Output high voltage
VOH IOH = -4mA 1, 2, 3 2.4
V
Output low voltage
VOL IOL = 4 mA 1, 2, 3
0.4 V
1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open.
2. One Bank operation.
3. Input signals are changed once per one clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals are VIH or VIL fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current. Self refresh should only be used at temperatures below 70 °C.
01.07.05 REV 4
All data sheets are subject to change without notice 4
©2005 Maxwell Technologies
All rights reserved.

4페이지










48SD1616 전자부품, 판매, 대치품
256Mb (4-Meg X 16-Bit X 4-Banks) SDRAM
Pin Functions:
48SD1616
www.DataSheet4U.com
CLK (INPUT PIN): CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS (INPUT PIN): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS AND WE (INPUT PINS): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operations section.
A0 TO A12 (INPUT PINS): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read
or write command cycle CLK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are pre-
charged. But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1
(BS) is pre charged. For details refer to the command operation section.
BA0/BA1 (INPUT PINS): BA0/BA1 are bank select signals (BS). The memory array of the 48SD1616 is divided
into bank 0, bank 1, bank 2 and bank 3. The 48SD1616 contains 8192-row X 512-column X 16-bit. If BA0
and BA1 is Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected. If BA0 is High and
BA1 is Low, bank 2 is selected. If BAO is High and BA1 is High, bank 3 is selected.
CKE (INPUT PIN): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising
edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode,
clock suspend mode and self refresh mode1.
DQMU/DQML (INPUT PINS): DQMU/DQML control input/output buffers
Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the
output buffer becomes Low-Z. ( The latency of DQMU/DQML during reading is 2 clock cycles.)
Write operation: If DQMU/DQML is High, the previous data is held ( the new data is not written). If the
DQMU/DQML is Low, the data is written. ( The latency of DQMU/DQML during writing is 0 clock cycles.)
DQ0 TO DQ15 (DQ PINS): Data is input to and output from these pins ( DQ0 to DQ15).
VCC AND VCCQ (POWER SUPPLY PINS): 3.3V is applied. ( VCC is for the internal circuit and VCCQ is for the output
buffer.)
VSS AND VSSQ (POWER SUPPLY PINS): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
1. Self refresh should only be used at temperatures below 70 °C.
01.07.05 REV 4
All data sheets are subject to change without notice 7
©2005 Maxwell Technologies
All rights reserved.

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부품번호상세설명 및 기능제조사
48SD1616

256 Mb SDRAM 4-Meg X 16-Bit X 4-Banks

Maxwell Technologies
Maxwell Technologies

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