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PDF LS2051 Data sheet ( Hoja de datos )
| Número de pieza | LS2051 | |
| Descripción | 8-Bit MCU | |
| Fabricantes | HuNan Hochip Times Microelectronics | |
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LS2051 (also refer to LS4051) is high performance eight bit microcomputer designed and
manufactured by our company and is compatible with MCS-51 instruction set, and its internal
function, pin function, pin configuration, and electrical characteristics of pins are compatible
with AT89C2051. LS2051 supports simultaneous operation of two independent or associated
programs. The performance when only one program is executed is 1.27 times of that of
AT89C2051, and the processing capacity is 2.55 times of AT89C2051 when two programs are
executed simultaneously.
Features
z Compatible with MCS-51 instruction set，pins are compatible with AT89C2051.
z 2/4KB internal flash program memory, Endurance: 2000 times erase/write cycles.
z 3.0V to 5.5V operating range.
z 0Hz to 24 MHz frequencies.
z Two-level of Encryption of Program Memory.
z 128×8B internal SRAM.
z 15 programmable I/O ports，20mA sink current，drives LED directly.
z Six interrupt sources.
z Two 16-bit timer and counter.
z One programmable UART.
z SPI programming interface.
z One high-resolution on-chip Analog Comparator.
z Low power idle and power-down modes.
Description
LS2051 contains 2K bytes of program memory (LS4051 contains 4K bytes), 128 byte of
data memory (SRAM), two 16-bit timer/counter, one five-vector secondary interrupt
architecture , a single-kernel for execute two programs, fifteen IO ports, a full duplex serial port,
a high-accuracy on-chip analogy comparator, oscillator and clock circuitry.
The operating range of LS2051 is 0Hz to 24MHz, and supports the idle power saving
mode and the power-down power saving mode which are software selectable. The idle mode
stops the CPU, while allowing the SRAM, timer/counter, serial port and interrupt machine and
the power-down system to continue functioning. The power-down mode saves the SRAM
contents but freezes oscillator and turns all the internal clocks off.
LS2051 achieves the function of double kernels, that is, it can execute one programming
singly, and it can also execute associated or non-associated two programs concurrently. The
performance of executing one program is 1.27 times of compatible chips, and that of
1
Update Date 5/27/2008-1-16
HuNan Hochip Times Microelectronics Co.,Ltd
1 page  
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P1
90H
11111111
TCON
TMOD
88H
00000000 00000000
SP
80H
00000111
TL0
00000000
0
DPL
00000000
TL1
0000000
0
DPH
0000000
0
TH0
0000000
0
TH1
0000000
0
97H
8FH
PCON
0XXX000
0
87H
Table 2: SFR Map and Reset Values
Note: IE ‘s d7 bit of Special Register is the interrupt enable bit for the main or first program,
and d6 bit is the interrupt enable bit for the second program.
Restriction on Some Instructions
The instruction system of LS2051 is compatible with MCS-51, but one should pay
attention to the following two restrictions when using LS2051 to develop application programs.
1、MOVX Related Instructions, Data Memory
The internal data memory of LS2051 is 128 bytes, the depth of stack is 128bytes,
accessing to the external data memory is not supported in LS2051, nor is the external program
memory. Therefore, no MOVX related instructions should be included in application programs.
A typical 51 assembler will still assemble such instructions even if they read and/or write
external memories. Users should know the physical features and limitations of LS2051 and
adjust instructions correspondingly.
2、Branching Instructions
The unconditional branching instructions , such as LCALL, LJMP, ACALL, AJMP, SJMP
and JMP @A+DPTR, are executed correctly only when the destination branching addresses
fall within 000H to 7FF, otherwise programs might go wrong.
The restrictions of conditional branching instructions, such as CJNE, DJNZ, JB, JNB, JC,
JNC, JBC, JZ and JNZ, are the same as that of unconditional branching instructions.
Other Restrictions
z The reset time should be over 100us when chips are power-on and/or waked from
power-down mode.
z It won’t response to an interrupt when the interrupt service for the interrupt is suspended.
z If idle mode is entered during an interrupt is being served, the idle mode can not be
waked up by the interrupt.
5
Update Date 5/27/2008-1-16
HuNan Hochip Times Microelectronics Co.,Ltd
5 Page 
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Notes ：
Under the stable circumstance (not instant), IOL is restricted the following
z The max allowable value of each port IOL is 20mA.
z The max sum of all the output port IOL is 80mA.
z If IOL exceeds test condition allowable value, and then VOL may exceed allowable value
by relatively, but it can guarantee port value will exceed value gained from test condition
as in Table 5.
Instruction set
Mnemonics definition table
In order to convenience the description to LS2051, the mnemonics are as table 6.
Mnemonics
Rn
Direct
@Ri
#data
#data16
Addr16
Addr11
Rel
bit
Description
Register R7±R0 of the currently selected Register Bank.
8-bit internal data location's address. This could be an Internal Data RAM location (0±127)
or a SFR [i.e., I/O port, control register, status register, etc. (128±255)].
8-bit internal data RAM location (0±255) addressed indirectly through register R1 or R0.
8-bit constant included in instruction.
16-bit constant included in instruction.
16-bit destination address. Used by LCALL & LJMP. A branch can be anywhere within the
64K-byte Program Memory address space.
11-bit destination address. Used by ACALL & AJMP. The branch will be within the same
2K-byte page of program memory as the first byte of the following instruction
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is b128 to a127 bytes relative to first byte of the following instruction.
Direct Addressed bit in Internal Data RAM or Special Function Register.
Table 6: Mnemonics Descriptions
Instructions
LS2051 instructions and their operations are show in Table 7.
Instruction
Byte
ARITHMETIC OPERATIONS
Oscillator
Period
Description
1 ADD A,Rn
2 ADD A,direct
3 ADD A,@Ri
1 12
2 12
1 12
Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
4 ADD A,#data
2 12
Add immediate data to Accumulator
11
Update Date 5/27/2008-1-16
HuNan Hochip Times Microelectronics Co.,Ltd
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet LS2051.PDF ] | |
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