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PDF R5S76700 Data sheet ( Hoja de datos )
| Número de pieza | R5S76700 | |
| Descripción | 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0437-0100
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32
SH7670 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family / SH7670 Series
SH7670
SH7671
SH7672
SH7673
R5S76700
R5S76710
R5S76720
R5S76730
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date: Nov. 14, 2007
1 page  
How to Use This Manual
www.DataSheet4U.com
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the SH7670 Group. Before using any of the
documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type
Data Sheet
Hardware Manual
Software Manual
Application Note
Renesas Technical
Update
Contents
Document Title
Document No.
Overview of hardware and electrical
characteristics
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
SH7670 Group
Hardware Manual
This manual
Detailed descriptions of the CPU
and instruction set
SH-2A, SH-2A FPU
Software Manual
REJ09B0051
Examples of applications and
sample programs
The latest versions are available from our
web site.
Preliminary report on the
specifications of a product,
document, etc.
Rev. 1.00 Nov. 14, 2007 Page v of xxvi
5 Page 
5.2.1 Input/Output Pins.............................................................................................. 113
5.2.2
5.2.3
Types of Reset ........................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m........ 113
Power-On Reset ................................................................................................ 114
5.2.4 Manual Reset .................................................................................................... 116
5.3 Address Errors .................................................................................................................. 117
5.3.1 Address Error Sources ...................................................................................... 117
5.3.2 Address Error Exception Handling ................................................................... 118
5.4 Register Bank Errors......................................................................................................... 119
5.4.1 Register Bank Error Sources............................................................................. 119
5.4.2 Register Bank Error Exception Handling ......................................................... 119
5.5 Interrupts........................................................................................................................... 120
5.5.1 Interrupt Sources............................................................................................... 120
5.5.2 Interrupt Priority Level ..................................................................................... 121
5.5.3 Interrupt Exception Handling ........................................................................... 122
5.6 Exceptions Triggered by Instructions ............................................................................... 123
5.6.1 Types of Exceptions Triggered by Instructions ................................................ 123
5.6.2 Trap Instructions ............................................................................................... 124
5.6.3 Slot Illegal Instructions ..................................................................................... 124
5.6.4 General Illegal Instructions............................................................................... 124
5.6.5 Integer Division Instructions............................................................................. 125
5.6.6 Floating-Point Operation Instruction ................................................................ 126
5.7 When Exception Sources Are Not Accepted .................................................................... 127
5.8 Stack Status after Exception Handling Ends..................................................................... 128
5.9 Usage Notes ...................................................................................................................... 130
5.9.1 Value of Stack Pointer (SP) .............................................................................. 130
5.9.2 Value of Vector Base Register (VBR) .............................................................. 130
5.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ..... 130
Section 6 Interrupt Controller (INTC) ...............................................................131
6.1 Features............................................................................................................................. 131
6.2 Input/Output Pins.............................................................................................................. 133
6.3 Register Descriptions........................................................................................................ 134
6.3.1 Interrupt Priority Registers 01, 02, 06 to 16
(IPR01, IPR02, IPR06 to IPR16) ...................................................................... 135
6.3.2 Interrupt Control Register 0 (ICR0).................................................................. 137
6.3.3 Interrupt Control Register 1 (ICR1).................................................................. 138
6.3.4 IRQ Interrupt Request Register (IRQRR)......................................................... 139
6.3.5 Bank Control Register (IBCR).......................................................................... 141
6.3.6 Bank Number Register (IBNR)......................................................................... 142
6.4 Interrupt Sources............................................................................................................... 143
Rev. 1.00 Nov. 14, 2007 Page xi of xxvi
11 Page | ||
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| PDF Descargar | [ Datasheet R5S76700.PDF ] | |
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