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Ordering number : ENN6860

CMOS IC

LC75864E, 75864W

1/4 Duty LCD Display Drivers with Key Input Function

Overview

The LC75864E and LC75864W are 1/4 duty LCD display

drivers that can directly drive up to 96 segments and can

control up to four general-purpose output ports. These

products also incorporate a key scan circuit that accepts

input from up to 30 keys to reduce printed circuit board

wiring.

Features

• Key input function for up to 30 keys (A key scan is

performed only when a key is pressed.)

• 1/4 duty - 1/2 bias and 1/4 duty - 1/3 bias drive schemes

can be controlled from serial data (up to 96 segments).

• Sleep mode and all segments off functions that are

controlled from serial data

• Segment output port/general-purpose output port

function switching that is controlled from serial data

• Serial data I/O supports CCB format communication

with the system controller.

• Direct display of display data without the use of a

decoder provides high generality.

• Independent VLCD for the LCD driver block

(VLCD can be set to in the range VDD - 0.5 to 6.0 volts.)

• Provision of an on-chip voltage-detection type reset

circuit prevents incorrect displays.

• RC oscillator circuit

Package Dimensions

unit: mm

3156-QIP48E

[LC75864E]

17.2

14.0

1.5 1.0 0.35

36

37

1.6

1.5

25

24

0.15

48

1

13

12

0.1

2.7

0.8

unit: mm

3163A-SQFP48

15.6

SANYO: QIP48E

[LC75864W]

0.75

36

37

9.0

7.0

0.5 0.18

0.75 0.15

25

24

48

1

13

12

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus

addresses are controlled by SANYO.

0.5 0.5

SANYO: SQFP48

Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft’s

control systems, or other applications whose failure can be reasonably expected to result in serious

physical and/or material damage. Consult with your SANYO representative nearest you before using

any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products specifications of any and all SANYO products described or contained

herein.

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

D2501TN (OT) No. 6860-1/26

LC75864E, 75864W

Electrical Characteristics for the Allowable Operating Ranges

Parameter

Symbol

Conditions

min

Hysteresis

Power-down detection voltage

Input high level current

Input low level current

Input floating voltage

Pull-down resistance

Output off leakage current

Output high level voltage

Output low level voltage

VH

VDET

IIH

IIL

VIF

RPD

IOFFH

VOH1

VOH2

VOH3

VOH4

VOL1

VOL2

VOL3

VOL4

VOL5

VMID1

CE, CL, DI, KI1 to KI5

CE, CL, DI: VI = 6.0 V

CE, CL, DI: VI = 0 V

KI1 to KI5

KI1 to KI5: VDD = 5.0 V

DO: VO = 6.0 V

KS1 to KS6: IO = –500 µA

P1 to P4: IO = –1 mA

S1 to S24: IO = –20 µA

COM1 to COM4: IO = –100 µA

KS1 to KS6: IO = 25 µA

P1 to P4: IO = 1 mA

S1 to S24: IO = 20 µA

COM1 to COM4: IO = 100 µA

DO: IO = 1 mA

COM1 to COM4: 1/2 bias, IO = ±100 µA

2.5

–5.0

50

VLCD – 1.0

VLCD – 1.0

VLCD – 1.0

VLCD – 1.0

0.2

1/2 VLCD –

1.0

VMID2 S1 to S24: 1/3 bias, IO = ±20 µA

2/3 VLCD –

1.0

Output middle level voltage*2

VMID3 S1 to S24: 1/3 bias, IO = ±20 µA

1/3 VLCD –

1.0

VMID4 COM1 to COM4: 1/3 bias, IO = ±100 µA

2/3 VLCD –

1.0

VMID5 COM1 to COM4: 1/3 bias, IO = ±100 µA

1/3 VLCD –

1.0

Oscillator frequency

Current drain

fOSC

IDD1

IDD2

ILCD1

ILCD2

ILCD3

OSC: ROSC = 43 kΩ, COSC = 680 pF

VDD: Sleep mode

VDD: VDD = 6.0 V, output open, fOSC = 50 kHz

VLCD: Sleep mode

VLCD: VLCD = 6.0 V, output open, 1/2 bias, fOSC = 50 kHz

VLCD: VLCD = 6.0 V, output open, 1/3 bias, fOSC = 50 kHz

40

Note: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)

Ratings

typ

0.1 VDD

3.0

max

3.5

5.0

100

VLCD – 0.5

0.05 VDD

250

6.0

VLCD – 0.2

0.5 1.5

1.0

1.0

1.0

0.1 0.5

1/2 VLCD +

1.0

2/3 VLCD +

1.0

1/3 VLCD +

1.0

2/3 VLCD +

1.0

1/3 VLCD +

1.0

50 60

100

270 540

5

100 200

60 120

Unit

V

V

µA

µA

V

kΩ

µA

V

V

V

kHz

µA

VLCD1

VLCD2

VLCD

To the common segment driver

Excluding these resistors.

Figure 1

No. 6860-4/26

Pin Functions

Pin Pin No.

S1/P1 to S4/P4

S5 to S22

1 to 4

5 to 22

COM1

COM2

COM3

COM4

23

24

25

26

LC75864E, 75864W

Function

Segment outputs for displaying the display data transferred by serial data

input.

The S1/P1 to S4/P4 pins can be used as general-purpose output ports

under serial data control.

Common driver outputs

The frame frequency fO is given by: fO = (fOSC/512) Hz.

Active

Handling

I/O when unused

— O Open

— O Open

KS1/S23

KS2/S24

KS3 to KS6

27

28

29 to 32

Key scan outputs

Although normal key scan timing lines require diodes to be inserted in the

timing lines to prevent shorts, since these outputs are unbalanced CMOS

transistor outputs, these outputs will not be damaged by shorting when

these outputs are used to form a key matrix. The KS1/S23 and KS2/S24

pins can be used as segment outputs when so specified by the control data.

—

O Open

KI1 to KI5

OSC

CE

CL

DI

DO

TEST

VLCD1

VLCD2

VDD

VLCD

VSS

33 to 37

44

46

47

48

45

43

40

Key scan inputs

These pins have built-in pull-down resistors.

Oscillator connection

An oscillator circuit is formed by connecting an external resistor and

capacitor at this pin.

Serial data interface connections to the controller. Note that DO, being an

open-drain output, requires a pull-up resistor.

CE: Chip enable

CL: Synchronization clock

DI: Transfer data

DO: Output data

This pin must be connected to ground.

Used for applying the LCD drive 2/3 bias voltage externally. Must be

connected to VLCD2 when a 1/2 bias drive scheme is used.

H I GND

— I/O VDD

HI

I GND

—I

— O Open

—I

—

— I Open

Used for applying the LCD drive 1/3 bias voltage externally. Must be

41 connected to VLCD1 when a 1/2 bias drive scheme is used.

— I Open

38

Logic block power supply connection. Provide a voltage of between 4.5 and

6.0 V.

—

—

—

LCD driver block power supply connection. Provide a voltage of between

39 VDD – 0.5 and 6.0 V.

——

—

42 Power supply connection. Connect to ground.

——

—

No. 6860-7/26

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