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PDF R5F7136 Data sheet ( Hoja de datos )
| Número de pieza | R5F7136 | |
| Descripción | 32-Bit RISC Microcomputer SuperH RISC engine Family | |
| Fabricantes | Renesas Technology | |
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REJ09B0402-0200
The revision list can be viewed directly bywww.DataSheet4U.com
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7137 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7136 R5F7136
SH7137 R5F7137
Rev.2.00
Revision Date: Sep. 10, 2008
1 page  
Configuration of This Manual
www.DataSheet4U.com
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.00 Sep. 10, 2008 Page v of xxvi
5 Page 
5.5.2 Trap Instructions ..................................................................................................... 85
5.5.3 Illegal Slot Instructions ...............................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 86
5.5.4 General Illegal Instructions..................................................................................... 86
5.6 Cases when Exceptions are Accepted .................................................................................. 87
5.7 Stack States after Exception Handling Ends ........................................................................ 88
5.8 Usage Notes ......................................................................................................................... 90
5.8.1 Value of Stack Pointer (SP) .................................................................................... 90
5.8.2 Value of Vector Base Register (VBR) .................................................................... 90
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 90
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 91
Section 6 Interrupt Controller (INTC) .................................................................93
6.1 Features................................................................................................................................ 93
6.2 Input/Output Pins ................................................................................................................. 95
6.3 Register Descriptions ........................................................................................................... 96
6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 97
6.3.2 IRQ Control Register (IRQCR) .............................................................................. 98
6.3.3 IRQ Status register (IRQSR) ................................................................................ 100
6.3.4 Interrupt Priority Registers A, D to F, and H to M
(IPRA, IPRD to IPRF, and IPRH to IPRM).......................................................... 103
6.4 Interrupt Sources................................................................................................................ 106
6.4.1 External Interrupts ................................................................................................ 106
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 107
6.4.3 User Break Interrupt ............................................................................................. 107
6.5 Interrupt Exception Handling Vector Table....................................................................... 108
6.6 Interrupt Operation............................................................................................................. 112
6.6.1 Interrupt Sequence ................................................................................................ 112
6.6.2 Stack after Interrupt Exception Handling ............................................................. 115
6.7 Interrupt Response Time.................................................................................................... 115
6.8 Data Transfer with Interrupt Request Signals .................................................................... 117
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation
and CPU Interrupts ............................................................................................... 118
6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation,
but Not CPU Interrupts ......................................................................................... 118
6.8.3 Handling Interrupt Request Signals as Sources for CPU Interrupts,
but Not DTC Activation........................................................................................ 119
6.9 Usage Note......................................................................................................................... 119
Rev. 2.00 Sep. 10, 2008 Page xi of xxvi
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