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PDF AOZ1015 Data sheet ( Hoja de datos )
| Número de pieza | AOZ1015 | |
| Descripción | EZBuck 1.5A Synchronous Buck Regulator | |
| Fabricantes | Alpha and Omega Semiconductors | |
| Logotipo |  |
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AOZ1015
www.DataSheet4U.com
EZBuck™ 1.5A Synchronous Buck Regulator
General Description
The AOZ1015 is a high efficiency, simple to use, 1.5A
buck regulator. The AOZ1015 works from a 4.5V to
16V input voltage range, and provides up to 1.5A of
continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1015 comes in an SO-8 package and is rated
over a -40°C to +85°C ambient temperature range.
Features
● 4.5V to 16V operating input voltage range
● 130mΩ internal PFET switch for high efficiency:
up to 95%
● Internal Schottky diode
● Internal soft start
● Output voltage adjustable to 0.8V
● 1.5A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Short-circuit protection
● Under voltage lockout
● Output over voltage protection
● Thermal shutdown
● Small size SO-8 package
Applications
● Point of load DC/DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment
Typical Application
VIN
C1
22µF Ceramic
From µPC
R1
C5 C2
VIN
EN AOZ1015
COMP
LX
FB
AGND PGND
L1
4.7µH
VOUT
R2
C4, C6
22µF x 2
Ceramic
R3
Rev. 1.2 September 2007
Figure 1. 3.3V/1.5A Buck Regulator
www.aosmd.com
Page 1 of 15
1 page  
AOZ1015
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
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Light Load (DCM) Operation
Vin
ripple
0.1V/div
Vo
ripple
20mV/div
IL
1A/div
VLX
10V/div
Full Load (CCM) Operation
Vin
ripple
0.1V/div
Vo
ripple
20mV/div
IL
1A/div
VLX
10V/div
1µs/div
1µs/div
Startup to Full Load
Vin
10V/div
Vo
1V/div
Full Load to Turnoff
Vin
10V/div
Iin
0.5A/div
400µs/div
50% to 100% Load Transient
400µs/div
Light Load to Turnoff
Vo
1V/div
Iin
0.5A/div
100µs/div
Vo
Ripple
50mV/div
Io
1A/div
1s/div
Vin
5V/div
Vo
1V/div
Iin
0.5A/div
Rev. 1.2 September 2007
www.aosmd.com
Page 5 of 15
5 Page 
AOZ1015
The previous equation above can also be simplified to:
CC
=
C-----O------×-----R-----L-
RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1015 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor
and load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the PGND pin of the
AOZ1015, to the LX pins of the AOZ1015. Current flows
in the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and PGND pin of the AOZ1015.
In the AOZ1015 buck regulator circuit, the two major
power dissipating components are the AOZ1015 and
the output inductor. The total power dissipation of
converter circuit can be measured by input power minus
output power.
P total _loss = V IN × I IN – V O × I O
The power dissipation of the inductor can be approxi-
mately calculated by output current and DCR of inductor.
P inductor _loss = IO2 × R inductor × 1.1
The actual AOZ1015 junction temperature can be
calculated with power dissipation in the AOZ1015 and
thermal impedance from junction to ambient.
T junction = (P total _loss–P inductor _loss) × Θ
+ + T ambient
The maximum junction temperatuwrewowf .tDhea tAaOS Zh e10e1t 45Uis. c o m
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for the maximum
load current of the AOZ1015 under different ambient
temperatures.
The thermal performance of the AOZ1015 is strongly
affected by the PCB layout. Extra care should be taken
by users during the design process to ensure that the IC
will operate under the recommended environmental
conditions.
Several layout tips are listed below for the best electronic
and thermal performance. Figure 3 illustrates a single
layer PCB layout example as reference.
1. Do not use thermal relief connection to the VIN and
the PGND pins. Pour a maximized copper area to the
PGND pin and the VIN pin to help thermal dissipation.
2. The input capacitors should be connected as close
as possible to the VIN and PGND pins.
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin. In this case, a decoupling
capacitor should be connected between VIN and
AGND.
4. Make the current trace from LX pins to L to CO to the
PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
6. The two LX pins are connected to the internal PFET
drain. They are low resistance thermal conduction
path and a noisy switching node. Connecting a
copper plane to the LX pin to help thermal dissipa-
tion. This copper plane should not be too large
otherwise switching noise may be coupled to other
parts of the circuit.
7. Keep sensitive signal traces such as trace
connecting FB and COMP away from the LX pins.
Rev. 1.2 September 2007
www.aosmd.com
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AOZ1015.PDF ] | |
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