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PDF AOZ1021 Data sheet ( Hoja de datos )
| Número de pieza | AOZ1021 | |
| Descripción | EZBuck 3A Synchronous Buck Regulator | |
| Fabricantes | Alpha and Omega Semiconductors | |
| Logotipo |  |
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AOZ1021
EZBuck™ 3A Synchronous Buck Regulator
General Description
The AOZ1021 is a synchronous high efficiency, simple
to use, 3A buck regulator. The AOZ1021 works from a
4.5V to 16V input voltage range, and provides up to 3A
of continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1021 comes in an SO-8 packages and is rated
over a -40°C to +85°C ambient temperature range.
Features
● 4.5V to 16V operating input voltage range
● Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ Internal low-side switch
● High efficiency: up to 95%
● Internal soft start
● 1.5% initial output accuracy
● Output voltage adjustable to 0.8V
● 3A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Pre-bias start-up
● Short-circuit protection
● Thermal shutdown
● Small size SO-8 package
Applications
● Point of load DC/DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment
Typical Application
VIN
C1
22μF
Ceramic
10kΩ
VIN
EN
AOZ1021 LX
COMP
RC
FB
CC
AGND
PGND
L1 4.7μH
R1
R2
VOUT
C2, C3
22μF Ceramic
Rev. 1.7 November 2010
Figure 1. 3.3V/3A Buck Regulator
www.aosmd.com
Page 1 of 15
1 page  
AOZ1021
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
1s/div
1s/div
Startup to Full Load
Vin
10V/div
Short Circuit Protection
Vo
2V/div
1ms/div
lin
1A/div
50% to 100% Load Transient
Vo ripple
100mV/div
4ms/div
Short Circuit Recovery
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
VLX
10V/div
Vo
2V/div
IL
2A/div
VLX
10V/div
100s/div
lo
1A/div
10ms/div
Vo
2V/div
IL
2A/div
Rev. 1.7 November 2010
www.aosmd.com
Page 5 of 15
5 Page 
AOZ1021
Thermal Management and Layout
Consideration
In the AOZ1021 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side NMOSFET.
Current flows in the second loop when the low-side
NMOSFET is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1021.
In the AOZ1021 buck regulator circuit, the major power
dissipating components are the AOZ1021 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
Ptotal_loss = VIN × IIN – VO × IO
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
Pinductor_loss = IO2 × Rinductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ1021 and thermal imped-
ance from junction to ambient.
Tjunction = (Ptotal_loss–Pinductor_loss) × ΘJA
The maximum junction temperature of AOZ1021 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1021 under different ambient
temperature.
The thermal performance of the AOZ1021 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1021A is a standard SO-8 package. Layout tips
are listed below for the best electric and thermal
performance. Figure 3 illustrates a PCB layout example
of the AOZ1021A.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
3. A ground plane is suggested. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the current trace from the LX pins to L to CO to
the PGND as short as possible.
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
6. The LX pins are connected to internal PFET drain.
They are a low resistance thermal conduction path
and the most noisy switching node. Connect a
copper plane to the LX pins to help thermal
dissipation. This copper plane should not be too
large otherwise switching noise may be coupled to
other parts of the circuit.
7. Keep sensitive signal traces far away from the LX
pins.
Rev. 1.7 November 2010
www.aosmd.com
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AOZ1021.PDF ] | |
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