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PDF AOZ1024D Data sheet ( Hoja de datos )
| Número de pieza | AOZ1024D | |
| Descripción | EZBuck 4A Synchronous Buck Regulator | |
| Fabricantes | Alpha and Omega Semiconductors | |
| Logotipo |  |
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AOZ1024D
EZBuck™ 4A Synchronwowuws.DBatuaSchkeeRt4eUg.cuomlator
General Description
The AOZ1024D is a synchronous high efficiency, simple
to use, 4A buck regulator. The AOZ1024D works from a
4.5V to 16V input voltage range, and provides up to 4A
of continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1024D comes in a DFN 5 x 4 package and is
rated over a -40°C to +85°C ambient temperature range.
Features
● 4.5V to 16V operating input voltage range
● Synchronous rectification: 100mΩ internal high-side
switch and 20mΩ internal low-side switch
● High efficiency: up to 95%
● Internal soft start
● 1.5% initial output accuracy
● Output voltage adjustable to 0.8V
● 4A continuous output current
● Fixed 500kHz PWM operation
● Cycle-by-cycle current limit
● Pre-bias start-up
● Short-circuit protection
● Thermal shutdown
● Small size DFN 5 x 4 package
Applications
● Point of load DC/DC conversion
● PCIe graphics cards
● Set top boxes
● DVD drives and HDD
● LCD panels
● Cable modems
● Telecom/networking/datacom equipment
Typical Application
VIN
C1
22µF
Ceramic
RC
CC
VIN
EN
AOZ1024D LX
COMP
FB
AGND PGND
L1 4.7µH
VOUT
R1
C2, C3
22µF
Ceramic
R2
Rev. 1.1 November 2007
Figure 1. 3.3V/4A Synchronous Buck Regulator
www.aosmd.com
Page 1 of 16
1 page  
AOZ1024D
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
www.DataSheet4U.com
Light Load Operation
Full Load (CCM) Operation
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
10V/div
1µs/div
1µs/div
Startup to Full Load
VIN
10V/div
Short Circuit Protection
LX
10V/div
Vo
2V/div
lin
1A/div
Vo
2V/div
lL
5A/div
1ms/div
50% to 100% Load Transient
100µs/div
Short Circuit Recovery
Vo Ripple
200mV/div
Vo
2V/div
100µs/div
lo
2A/div
2ms/div
IL
5A/div
Rev. 1.1 November 2007
www.aosmd.com
Page 5 of 16
5 Page 
AOZ1024D
The previous equation can also be simplified to:
CC
=
C-----O------×-----R-----L-
RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1024D buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor
and load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the lowside NMOSFET.
Current flows in the second loop when the lowside
NMOSFET is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input capaci-
tor, output capacitor, and PGND pin of the AOZ1024D.
In the AOZ1024D buck regulator circuit, the major power
dissipating components are the AOZ1024D and the
output inductor. The total power dissipation of converter
circuit can be measured by input power – output power.
Ptotal = V IN × IIN – V O × IO
The power dissipation of the inductor can be
approximately calculated by output current and DCR
of inductor.
P inductor = IO2 × R inductor × 1.1
The actual junction temperature can be calculated with
power dissipation in the AOZ1024D and thermal
impedance from junction to ambient.
T junction = (P total –P inductor _loss) × ΘJA
The maximum junction temperatuwrewowf.DAaOtaZS1h0e2e4t4DU.cisom
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1024D under different ambient
temperature.
The thermal performance of the AOZ1024D is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1024D is standard DFN5*4 package. Several
layout tips are listed below for the best electric and
thermal performance. Figure 3 on the next page
illustrates a PCB layout example of AOZ1024D.
1. The LX pins are connected to internal PFET and
NFET drains. They are low resistance thermal
conduction path and most noisy switching node.
Connected a large copper plane to LX pin to help
thermal dissipation. For full load (4A) application,
also connect the LX pads to the bottom layer by
thermal vias to enhance the thermal dissipation.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
4. A ground plane is preferred. If a ground plane is
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from LX pins to L to CO to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
7. Keep sensitive signal trace far away form the LX pins.
Rev. 1.1 November 2007
www.aosmd.com
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AOZ1024D.PDF ] | |
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