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부품번호 SH69P55A 기능
기능 OTP/MASK 8K 4-Bit Micro-controller
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SH69P55A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
SH69P55A/K55A
OTP/MASK 8K 4-Bit Micro-controller
With LCD Driver & 10-bit SAR ADC
Features
„ SH6610D-Based Single-Chip 4-bit Micro-Controller With
LCD Driver & 10-bit SAR ADC
„ OTP ROM: 8K X 16 bits (SH69P55A)
„ MASK ROM: 8K X 16 bits (SH69K55A)
„ RAM: 515X 4 bits
- 99 System Control Register
- 376 Data Memory
- 40 LCD RAM
„ Operation Voltage: 2.4V - 5.5V
- fOSC = 30k- 4MHz, VDD = 2.4V - 5.5V
- fOSC = 30k - 8MHz, VDD = 4.5V - 5.5V
„ 42 CMOS Bi-directional I/O Pins (Including one
open-drain output PortC.3)
„ Built-in Pull-high Resistor For PORTA - PORTK
„ 8-Level Stack (Including Interrupts)
„ Two 8-bit and One 16-bit Auto Re-loaded Timer/Counter
„ LCD Driver:
- 16 SEG X 8 COM (1/8 Duty, 1/4 Bias)
- 18 SEG X 6 COM (1/6 Duty, 1/3 Bias)
- 20 SEG X 4 COM (1/4 Duty, 1/3 Bias)
„ LED Driver:
- 8 SEG X 6 COM (1/6 Duty)
- 8 SEG X 5 COM (1/5 Duty)
- 8 SEG X 4 COM (1/4 Duty)
„ Powerful Interrupt Sources:
- Timer0 Interrupt
- Timer1 Interrupt
- Timer2 Interrupt
- External Interrupts (PORTB & PORTC Falling Edge
Interrupts, A/D Interrupt, Key Scan Interrupt)
„ Oscillator (Code Option)
- Crystal Oscillator: 32.768kHz, 400kHz - 8MHz
- Ceramic Resonator: 400kHz - 8MHz
- External RC Oscillator: 400kHz - 8MHz
- Internal RC Oscillator: 4MHz ±5%
„ One Built-in PLL Oscillator (1, 2, 4, 8MHz)
„ Instruction Cycle Time (4/fOSC)
„ 10 Channels 10-Bit Resolution Analog/Digital Converter
(ADC)
„ 2 Channel Tone Generators
„ Built-in Automatic Key Scanner
„ Zero Cross Detect Function for AC Power Line
„ Read ROM Data Table Function (RDT)
„ One Channel 8+2Bit PWM Output
„ Reset
- Built-in Watchdog Timer (WDT) [(Code Option)]
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR) [(Code Option)]
„ Two-Level Low Voltage Reset (LVR) (Code Option)
„ Two Low Power Operation Modes: HALT and STOP
„ OTP Type/Code Protection (SH69P55A)
„ MASK Type (SH69K55A)
„ 28-pin SOP package; 44-pin QFP package; 32-pin DIP
package
General Description
SH69P55A/69K55A is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, RAM, ROM, timer,
LCD/LED driver, I/O ports, watchdog timer, 10 channels 10-bit resolution ADC, low voltage reset, automatic key scan, PLL
and Zero Cross Detect function. The SH69P55A/69K55A is suitable for washing machine and micro-wave oven etc.
application.
1 V2.1




SH69P55A pdf, 반도체, 판매, 대치품
Block Diagram
www.DataSheet4U.com
SH69P55A/K55A
RESET/PORTC.3
Reset Circuit
PORTC.3
RAM
99 X 4 Bits
System Register
376 X 4 Bits
Data Memory
40X 4 Bits
LCD RAM
ROM
8196 X 16 Bits
WDT RC
Watch Dog
Timer
10ch X 10bits
ADC
1 X ( 8+2) Bits
PWM
VDD
GND
PORTJ.3 - 0/AN7 - AN4
PORTK.1 - 0
CPU
Power Circuit
PORTJ (4-bit)
PORTK (2-bit)
Tone generator 1
Tone generator 2
TIMER2
(16 Bits)
TIMER1
(8 Bits)
TIMER 0
(8 Bits)
Oscillator
PORTC.2 - 0
PORTA (4-bit)
PORTD (4-bit)
PORTB (4-bit)
PORTE (4-bit)
PORTF (4-bit)
PORTH (4-bit)
PORTG (4-bit)
PORTI (4-bit)
OSCI/PORTC.2
OSCO/PORTC.1
PORTC.0/PLL_C
PORTA.3 - 0/SEG4 - SEG1/
LED_S4 - LED_S1/
KEY_I4 - KEY_I1
PORTD.3 - 0/COM1 - COM4/
LED_C1 - LED_C4/
KEY_O1 - KEY_O4
PORTB.3 - 0/AN3 - AN0
PORTE.3 - 0/COM5 - COM8/
LED_C5 - LED_C6/
SEG20 - SEG17
PORTF.3 - 0/SEG8 - SEG5/
LED_S8 - LED_S5/KEY_I5
PORTH.3 - 0/SEG16 - SEG13
PORTG.3 - 0/T2, T0, VREF/
TONE/PWM/AN8 - AN9
PORTI.3 - 0/SEG12 - SEG9
4

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SH69P55A 전자부품, 판매, 대치품
www.DataSheet4U.com
SH69P55A/K55A
Functional Descriptions
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bit:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can address only 4K program ROM
address. (Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, ADCM, ADD, ADDM,
SBC, SBCM, SUB, SUBM, ADI, ADIM, SBI, SBIM)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, ANDM, EOR, EORM, OR, ORM,
ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BNZ, BC, BNC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or call instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register,
or data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The TBR and AC are placed
by an offset address in program ROM. TJMP instruction
branch into address ((PC11 - PC8) X (28) + (TBR, AC)). The
address is determined by RTNW to return look-up value
into (TBR, AC). ROM code bit7-bit4 is placed into TBR and
bit3-bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range is
000H--3FFH. Pseudo index address (INX) is used to read
or write Data memory, then RAM address bit9 - bit0 which
comes from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents
of CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into
13 bits X 8 levels. The stack is operated on a first-in,
last-out basis and returned sequentially to the PC by the
return instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will
be shifted out, that program execution may enter an
abnormal state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU entering STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register: $000 - $02F, $380 - $3AF, $3C0 - $3C2
Data memory: $030 - $1A7
LCD RAM space: $300 - $313, $320 - $333
RAM Bank Table:
Bank 0
B=0
Bank 1
B=1
Bank 2
B=2
Bank 3
B=3
Bank 4
B=4
Bank 5
B=5
Bank 6
B=6
Bank 7
B=7
$000 - $07F $080 - $0FF $100 - $17F $180 - $1FF $200 - $27F $280 - $2FF $300 - $37F
$380 - $3AF,
$3C0 - $3C2
Where, B: RAM bank bit use in instructions
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부품번호상세설명 및 기능제조사
SH69P55

OTP 8K 4-Bit Micro-controller

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SH69P55A

Application Note

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