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28C16B 데이터시트 PDF




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기능 M28C16B
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28C16B 데이터시트, 핀배열, 회로
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M28C16B
M28C17B
16 Kbit (2K x 8) Parallel EEPROM
With Software Data Protection
PRELIMINARY DATA
s Fast Access Time: 90 ns at VCC=5V
s Single Supply Voltage:
– 4.5 V to 5.5 V for M28CxxB
– 2.7 V to 3.6 V for M28CxxB-W
s Low Power Consumption
s Fast BYTE and PAGE WRITE (up to 64 Bytes)
– 3 ms at VCC=4.5 V
– 5 ms at VCC=2.7 V
s Enhanced Write Detection and Monitoring:
– Data Polling
– Toggle Bit
– Page Load Timer Status
s JEDEC Approved Bytewide Pin-Out
s Software Data Protection
s 100000 Erase/Write Cycles (minimum)
s Data Retention (minimum): 40 Years
DESCRIPTION
The M28C16B and M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabri-
cated with STMicroelectronics’ proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation, and
require a single voltage supply.
Table 1. Signal Names
A0-A10
Address Input
DQ0-DQ7
Data Input / Output
W Write Enable
E Chip Enable
G Output Enable
RB Ready/Busy (M28C17B only)
VCC
Supply Voltage
VSS Ground
PLCC32 (K)
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W M28C16B
M28C17B
E
RB
G (M28C17B only)
VSS
AI02816
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/17




28C16B pdf, 반도체, 판매, 대치품
M28C16B, M28C17B
Table 3. Operating Modes 1
Mode
E
Stand-by
1
Output Disable
X
Write Disable
X
Read
0
Write
0
Chip Erase
0
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%.
G
X
1
X
0
1
V
W
X
X
1
1
0
0
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DQ0-DQ7
Hi-Z
Hi-Z
Hi-Z
Data Out
Data In
Hi-Z
end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit func-
tions on DQ7 and DQ6.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
than the tWLQ5H value (as specified in Table 10A).
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
1/tWLQ5H.
The internal write cycle can start at any instant af-
ter tWLQ5H. Once initiated, the write operation is in-
ternally timed, and continues, uninterrupted, until
completion.
All bytes must be located on the same page ad-
dress (A10-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are
Table 4A. Power-Up Timing1 for M28CxxB (5V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC VWI)
VWI Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28CxxB-W (3V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
tPUR
Time Delay to Read Operation
tPUW
Time Delay to Write Operation (once VCC VWI)
VWI Write Inhibit Threshold
Note: 1. Sampled only, not 100% tested.
4/17
Min.
3.0
Max.
1
10
4.2
Unit
µs
ms
V
Min.
1.5
Max.
1
15
2.5
Unit
µs
ms
V

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28C16B 전자부품, 판매, 대치품
Table 6A. Read Mode DC Characteristics for M28CxxB (5V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 4.5 to 5.5 V)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0 V VIN VCC
ILO Output Leakage Current
0 V VOUT VCC
ICC 1
Supply Current (TTL inputs)
Supply Current (CMOS inputs)
E = VIL, G = VIL , f = 5 MHz
E = VIL, G = VIL , f = 5 MHz
ICC1 1 Supply Current (Stand-by) TTL
E = VIH
ICC2 1 Supply Current (Stand-by) CMOS
E > VCC - 0.3V
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 2.1 mA
VOH Output High Voltage
Note: 1. All inputs and outputs open circuit.
IOH = -400 µA
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M28C16B, M28C17B
Min.
-0.3
2
2.4
Max.
10
10
30
25
Unit
µA
µA
mA
mA
1 mA
100 µA
0.8
VCC + 0.5
0.4
V
V
V
V
Table 6B. Read Mode DC Characteristics for M28CxxB-W (3V range)
(TA = 0 to 70 °C or -40 to 85 °C; VCC = 2.7 to 3.6 V)
Symbol
Parameter
Test Condition
ILI Input Leakage Current
0 V VIN VCC
ILO Output Leakage Current
0 V VOUT VCC
ICC 1 Supply Current (CMOS inputs)
E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V
E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V
ICC2 1 Supply Current (Stand-by) CMOS
E > VCC - 0.3V
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
IOL = 1.6 mA
VOH Output High Voltage
Note: 1. All inputs and outputs open circuit.
IOH = -400 µA
Min.
-0.3
2
0.8 VCC
Max. Unit
10 µA
10 µA
8 mA
10 mA
20 µA
0.6 V
VCC + 0.5
0.2 VCC
V
V
V
cessive Write operations, up to tWLQ5H (defined in
Table 10A). The DQ5 line is held low to show
when this timer is running (hence showing that the
device has received one write operation, and is
waiting for the next). The DQ5 line is held high
when the counter has overflowed (hence showing
that the device is now starting the internal write to
the memory array).
7/17

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