LC78601E - Compact Disc Player DSP with Built-in Microcontroller

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LC78601E 기능

기능

Compact Disc Player DSP with Built-in Microcontroller

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Sanyo Semicon Device

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Ordering number : EN6020

CMOS IC

LC78601E

Compact Disc Player DSP with

Built-in Microcontroller

Overview

The LC78601E CMOS IC implements compact disc

player signal processing, servo control, LCD display, key

input acquisition, and remote controller processing

without requiring control by a separate microcontroller.

The basic functions provided include demodulation of the

EFM signal from the optical pickup, deinterleaving, error

detection and correction, 8× oversampling digital filters,

D/A converter (with built-in analog low-pass filter), LCD

driver, remote controller processing, key acquisition, and

control processing. Thus this IC can provide excellent

cost/performance characteristics when implementing a

low-end CD player.

Functions

• Implements CD play/pause, disc stop, track selection,

fast forward, reverse, repeat mode playback of 1 track or

the whole disc, programmed play (setup, play, and clear)

of up to 16 tracks, and random repeat play under the

control of key input or remote controller input.

<Signal-Processing Block>

• Slices an input high-frequency signal at an accurate

level, converts the EFM signal, and generates a clock

with an average frequency of 4.3218 MHz using a PLL

circuit that performs a phase comparison with an

internal VCO.

• Accurately generates not only the reference clock but

also all necessary internal timings using an external

16.9344MHz crystal.

• Controls the disc motor speed using a frame difference

signal created based on the reproduced clock signal and

a reference clock.

• Performs detection, protection, and interpolation for the

frame synchronizing signal to assure stable data readout.

• Demodulates the EFM signal, converting it to 8-bit

symbol data.

• Separates the subcode data from the EFM signal and

outputs that data to the internal control processing block.

• After applying a CRC check to the subcode Q signal,

outputs that signal to the internal control processing

block.

• Buffers the demodulated EFM signal data in internal

RAM and compensates for ±4 frames of jitter due to

disc speed fluctuations.

• Performs unscrambling and deinterleaving by reordering

the demodulated EFM signal data to the stipulated order.

• Performs error detection and correction and flag

processing (C1: dual errors, C2: dual errors)

• The C2 flags are set based on the C1 flags and the result

of the C2 processing, and the signal is interpolated or

previous value hold is applied based on the C2 flags.

Dual interpolation is adopted in the interpolation circuit.

Previous value hold is applied if two or more

consecutive errors are indicated by the C2 flags.

• Performs track jump, focus start, disc motor start/stop,

muting on/off, track count, and other operations under

control of the internal control processing block.

• Provides digital outputs.

• Generates D/A converter input signals with continuity

improved by 8× oversampling digital filters.

• Includes on-chip third-order noise shaper delta-sigma

D/A converters with built-in analog low-pass filter.

• Digital deemphasis circuit

• Adopts zero-cross muting.

• On-chip LCD drivers for 2-digit display plus play,

program, repeat, and random indicators

• On-chip bias voltage generator

• Key matrix circuit with 4 inputs and 2 outputs for an

8-key matrix

• Supports remote controller input.

Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft’s

control systems, or other applications whose failure can be reasonably expected to result in serious

physical and/or material damage. Consult with your SANYO representative nearest you before using

any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products specifications of any and all SANYO products described or contained

herein.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

D1898RM (OT) No. 6020-1/11

LC78601E

Electrical Characteristics at Ta = –20 to +75°C, VDD = 4.5 to 5.5 V, VSS = 0 V

Parameter

Current drain

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

Output off leakage current

Pull-up resistance

Pull-down resistance

Charge pump output current

Symbol

Applicable pins

Conditions

IDD

IIH1

IIH2

IIL1

IIL2

VOH1

VOH2

VOH3

VOH4

VOL1

VOL2

VOL3

VOL4

VOL5

IOFFH

IOFFL

RPU

RPD

IPDOH

IPDOL

VDD, XVDD, L/RVDD, VVDD

DEFI, 3 V/*5 V, EFMIN, TMOD, HFL,

TES, PUIN, *KEYI1 to 4, RMTSL1 to 3, VIN = VDD

REMOTE, CLOSE, *RES, DRF

LASER, FSTA, EFBAL, SP8

DEFI, 3 V/*5 V, EFMIN, TMOD, HFL,

TES, RMTSL2 to 3, REMOTE, *RES,

DRF

VIN = VDD

VIN = 0 V

PUIN, *KEYI1 to 4, RMTSL1, CLOSE

EFMO, CLV, TOFF, TGL, JP, LASER,

FSTA, EFBAL, SP8, FSEQ, PCK,

SLOF, SLED+, SLED–, EFLG, FSX,

*AMUTE

VIN = 0 V

IOH = –1 mA

S1 to 6

COM1 to 3

DOUT

EFMO, CLV, TOFF, TGL, JP, FSEQ,

PCK, SLOF, SLED+, SLED–,

*KEYO1 to 2, EFLG, FSX,

RMTSL2 to 3, *AMUTE

IOH = –0.02 mA

IOH = – 0.1 mA

IOH = –12 mA

IOL = 1 mA

*RANDOM

S1 to 6

COM1 to 3

DOUT

PDO, CLV, JP, *KEY01 to 2,

*RANDOM

IOL = 8 mA

IOL = 0.02 mA

IOL = 0.1 mA

IOL = 12 mA

VOUT = VDD

PDO, CLV, JP, *KEY01 to 2,

*RANDOM

VOUT = 0 V

PUIN, *KEYI1 to 4, RMTSL1, CLOSE,

*RES

LASER, FSTA, EFBAL, SP8

PDO

RISET = 68 kΩ

min

250

–5

–25

0.8 VDD

0.9 VDD

–5

–96

Ratings

typ

500

max

1000

–50 –100

0.2 VDD

0.1 VDD

100

80 96

–80 –64

1-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = L/RVDD = 5 V, VSS = L/RVSS = 0 V

Parameter

Symbol Applicable pins

Conditions

Total harmonic distortion

Dynamic range

Signal-to-noise ratio

Crosstalk

THD+N

S/N

LCHO, RCHO

1 kHz: 0dB data input

20kHz low-pass filter used (built-in AD725D)

1 kHz: –60dB data input

20kHz low-pass filter and A filter used (built-in AD725D)

1 kHz: 0dB data input

20kHz low-pass filter and A filter used (built-in AD725D)

1 kHz: 0dB data input

20kHz low-pass filter used (built-in AD725D)

Note: Measure in normal speed playback mode with the Sanyo 1-bit D/A converter block reference circuit.

Ratings

min typ

0.02

86 88

96 98

80 82

max

0.035

Unit

µA

kΩ

µA

Unit

No. 6020-4/11

4페이지

LC78601E

Continued from preceding page.

Pin No.

EFLG

50 FSX

51 *AMUTE

52 REMOTE

53 RMTSL2

54 LCHO

55 L/RVDD

56 L/RVSS

57 RCHO

58 CLOSE

59 RMTSL1

60 XOUT

61 XIN

62 XVDD

63 *RES

64 DRF

I/O Function

Monitor for C1, C2, single, and double error corrections.

O (Note that this output is only provided in test mode. This pin outputs a low level during normal

mode operation.)

Outputs a 7.35 kHz synchronizing signal that is generated by dividing the crystal oscillator output.

O (Note that this output is only provided in test mode. This pin outputs a low level during normal

mode operation.)

O Audio mute output signal

I Remote controller signal input

Remote controller identifier input (2). This pin functions as an output pin set to the low level

during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin

I/O switches to the high level. Therefore, applications that will set this pin high must connect an

external pull-up resistor to this pin.

O Left channel D/A converter output

— D/A converter power supply

— D/A converter ground. This pin must be connected to 0 V.

O Right channel D/A converter output

I Close switch detection input. A pull-up resistor is built in.

I Remote controller identifier input (1). A pull-up resistor is built in.

Connections for a 16.9344 crystal element

— Crystal oscillator circuit power supply

I IC reset input. Applications must set this pin low temporarily when power is first applied.

I DRF input. (Connected when an LA9250M is used.)

Note: The same potential must be connected to all the power supply pins (VDD, VVDD, L/RVDD, and XVDD).

Pin state during reset

Low output

—

Low output

Undefined

—

Undefined

—

Clock output

—

No. 6020-7/11

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부품번호	상세설명 및 기능	제조사
LC78601E	Compact Disc Player DSP with Built-in Microcontroller	Sanyo Semicon Device