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Ordering number : EN*5223

CMOS LSI

LC78621E

Compact Disc Player DSP

Preliminary

Overview

The LC78621E is a CMOS LSI that implements the signal

processing and servo control required by compact disk

players, laser disks, CD-V, CD-I and related products. The

LC78621E provides several types of signal processing,

including demodulation of the optical pickup EFM signal,

de-interleaving, error detection and correction, and digital

filters that can help reduce the cost of CD player units. It

also processes a rich set of servo system commands sent

from the control microprocessor. It also incorporates an

EFM-PLL circuit and a one-bit D/A converter.

Functions

• Input signal processing: The LC78621E takes an HF

signal as input, digitizes (slices) that signal at a precise

level, converts that signal to an EFM signal, and

generates a PLL clock with an average frequency of

4.3218 MHz by comparing the phases of that signal and

an internal VCO.

• Precise reference clock and necessary internal timing

generation using an external 16.9344 MHz crystal

oscillator

• Disk motor speed control using a frame phase difference

signal generated from the playback clock and the

reference clock

• Frame synchronization signal detection, protection and

interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit

symbol data

• Subcode data separation from the EFM demodulated

signal and output of that data to an external

microprocessor

• Subcode Q signal output to a microprocessor over the

serial I/O interface after performing a CRC error check

• Demodulated EFM signal buffering in internal RAM to

handle up to ±4 frames of disk rotational jitter

• Demodulated EFM signal reordering in the prescribed

order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error

correction scheme: dual C1 plus dual C2 correction)

• The LC78620E sets the C2 flags based on the C1 flags

and a C2 check, and then performs signal interpolation

or muting depending on the C2 flags. The interpolation

circuit uses a quadruple interpolation scheme. The

output value converges to the muting level when four or

more consecutive C2 flags occur.

• Support for command input from a control

microprocessor: commands include track jump, focus

start, disk motor start/stop, muting on/off and track

count (8 bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data

access

• Zero cross muting

• Supports the implementation of a double-speed dubbing

function.

• D/A converter outputs with data continuity improved by

8× oversampling digital filters. (These filters function as

4× oversampling filters during double-speed playback.)

• Built-in third-order ∑∆ D/A converters (PWM output)

• Built-in digital attenuator (8 bits – alpha, 239 steps)

• Built-in digital de-emphasis

• Built-in digital level and peak meter functions

• Support for bilingual applications

Features

• 80-pin QIP (miniature, reduced space package)

• Silicon gate CMOS process (for low power)

• 5 V single-voltage power supply (for use in portable

products)

Package Dimensions

unit: mm

3174-QFP80E

[LC78621E]

SANYO: QIP80E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

83095HA (OT) No. 5223-1/34

LC78621E

Continued from preceding page.

Parameter

Symbol

Conditions

min typ max

VOL (1)

EFMO, EFMO, CLV+, CLV–, V/P, FOCS, PCK, FSEQ,

TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX:

IOL = 1 mA

1

Output low-level voltage

VOL (2)

MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO,

TST10, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY,

WRQ, SQOUT, TST11, 16M, 4.2M, CONT, LASER:

IOL = 2 mA

0.4

VOL (3) DOUT: IOL = 12 mA

0.5

VOL (4) FST: IOL = 5 mA

0.75

Output off leakage current

VOL (5)

IOFF (1)

IOFF (2)

LCHP, RCHP, LCHN, RCHN: IOL = 1mA

PDO, CLV+, CLV–, JP+, JP–, FST: VOUT = 5 V

PDO, CLV+, CLV–, JP+, JP–: VOUT = 0 V

0.5

–5

2.0

5

Charge pump output current

IPDOH

IPDOL

PDO: RISET = 68 kΩ

PDO: RISET = 68 kΩ

100

–150

125

–125

150

–100

Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 kΩ (±5.0%) tolerance resistor.

Unit

V

V

V

V

V

µA

µA

µA

µA

One-Bit D/A Converter Analog Characteristics

at Ta = 25°C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V

Parameter

Symbol

Conditions

min typ max Unit

Total harmonic distortion

LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input,

THD + N using the 20 kHz low-pass filter (AD725D built in)

0.008

0.010

%

Dynamic range

LCHP, RCHP, LCHN, RCHN; 1 kHz: –60 dB data input,

DR using the 20 kHz low-pass filter and the A filter

84

(AD725D built in)

88

dB

Signal-to-noise ratio

LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input,

S/N using the 20 kHz low-pass filter and the A filter

(AD725D built in)

98

100

dB

Crosstalk

LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input,

CT using the 20 kHz low-pass filter (AD725D built in)

96

98

dB

Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal).

Figure 1 Command Input

No. 5223-4/34

LC78621E

Pin Functions

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Symbol

DEFI

TAI

PDO

VVSS

ISET

VVDD

FR

VSS

EFMO

EFMO

EFMIN

TEST2

CLV+

CLV–

V/P

FOCS

FST

FZD

HFL

TES

PCK

FSEQ

TOFF

TGL

THLD

TEST3

VDD

JP+

29 JP–

30 DEMO

31 TEST4

32 EMPH

33 LRCKO

34 DFORO

35 DFOLO

36 DACKO

37 TST10

38 ASDACK

39 ASDFIN

40 ASDFIR

41 ASLRCK

I/O Function

I Defect detection signal (DEF) input (Must be tied low if unused.)

I Test input. A pull-down resistor is built in.

O External VCO control phase comparator output

PLL pins

AI

Internal VCO ground. Normally 0 V.

PDO output current adjustment resistor connection

Internal VCO power supply.

AI VCO frequency range adjustment

Digital system ground. Normally 0 V.

O EFM signal inverted output

O Slice level control

EFM signal output

I EFM signal input

I Test input. A pull-down resistor is built in.

O Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV– is high

O Three-value output is also possible when specified by microprocessor command.

Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level

O during phase control.

O Focus servo on/off output. Focus servo is on when the output is low.

O Focus start pulse output. This is an open-drain output.

I Focus error zero cross signal input. (Must be tied low if unused.)

I Track detection signal input. This is a Schmitt input.

I Tracking error signal input. This is a Schmitt input.

O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.

Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM

O signal and the internally generated synchronization signal agree.

O Tracking off output

O Tracking gain switching output. Increase the gain when low.

O Tracking hold output

I Test input. A pull-down resistor is built in.

Digital system power supply.

O Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an

inward jump.

A high level output from JP– indicates acceleration during an inward jump or deceleration during an outward jump.

O Three-value output is also possible when specified by microprocessor command.

I Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in.

I Test input. A pull-down resistor is built in.

O De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk.

O Word clock output

O

Digital filter outputs

O

Right channel data output

Left channel data output

O Bit clock output

O Test output. Leave open. (Normally outputs a low level.)

I Bit clock input

I Anti-shock system inputs Left/right channel data input

I (Must be tied low if unused.) Test input. (Should be tied low for normal operation.)

I Word clock input

Continued on next page.

No. 5223-7/34

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