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LC78624E 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC78624E은 전자 산업 및 응용 분야에서
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부품번호 LC78624E 기능
기능 Compact Disc Player DSP
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LC78624E 데이터시트, 핀배열, 회로
Ordering number : EN5811
CMOS LSI
LC78624E
Compact Disc Player DSP
Overview
The LC78624E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players. Including an EFM-PLL and text decoder, the
LC78624E strictly limits functionality to basic signal
processing and servo system operation to achieve the best
cost-performance balance for low-end players. As basic
functions, the LC78624E provides demodulation of the
EFM signal from the optical pickup, de-interleaving, error
detection and correction, and processes servo commands
sent from the control microcontroller.
Functions
• Input signal processing: The LC78624E takes an HF
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
• Precise reference clock and necessary internal timing
generation using an external 16.9344 MHz crystal
oscillator
• Disk motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microcontroller
• Subcode Q signal output to a microcontroller over the
serial I/O interface after performing a CRC error check
(LSB first)
• Serial output to a microcontroller via the text decoder of
the song titles and other text data stored in the Subcode
R through W channels of the read-in area
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disk rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78624E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a dual-interpolation scheme. The previous
value is held if the C2 flags indicate errors two or more
times consecutively.
• Support for command input from a microcontroller:
commands include track jump, focus start, disk motor
start/stop, muting on/off and track count (8 bit serial
input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
access
• Zero cross muting
• Supports the implementation of a double-speed dubbing
function.
• Support for bilingual applications.
• General-purpose I/O ports: 5 pins
Features
• 64 pin QFP
• 5 V single-voltage power supply
Package Dimensions
unit: mm
3159-QFP64E
[LC78624E]
SANYO: QIP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
20698RM (OT) No. 5811-1/27




LC78624E pdf, 반도체, 판매, 대치품
LC78624E
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Current drain
Input high level current
Input low level current
Output high level voltage
Output low level voltage
Output off leakage current
Charge pump output current
Symbol
Conditions
IDD
IIH (1)
IIH (2)
IIL
VOH (1)
VOH (2)
VOH (3)
VOL (1)
VOL (2)
VOL (3)
IOFF (1)
IOFF (2)
IPDOH
IPDOL
VDD, XVDD, VVDD
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,
RWC, CQCK: TEST1, SCLK: VIN = VDD
TAI, TEST2 to TEST6, CS: VIN = VDD = 5.5 V
DEFI, EFMIN, COIN, RES, HFL, TES, SBCK,
RWC, CQCK: TAI, TEST1 to TEST6, CS, SCLK: VIN = 0 V
EFMO, CLV+, CLV, V/P, PCK, FSEQ, TOFF,
TGL, JP+, JP, EMPH, EFLG, FSX: IOH = –1 mA
TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M,
4.2M, CONT1 to CONT5: IOH = –0.5 mA
DOUT: IOH = –12 mA
EFMO, CLV+, CLV, V/P, PCK, FSEQ,
TOFF, TGL, JP+, JP, EMPH, EFLG, FSX:
IOL = 1 mA
TEST7 to TEST8, DQSY, SRDT, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT,
TST11, 16M, 4.2M, CONT1 to CONT5:
IOL = 2 mA
DOUT: IOL = 12 mA
PDO, CLV+, CLV, JP+, JP, CONT1 to CONT5:
VOUT = VDD
PDO, CLV+, CLV, JP+, JP, CONT1 to CONT5:
VOUT = 0 V
PDO: RISET = 68 k
PDO: RISET = 68 k
min
25
–5
4
4
4.5
–5
64
–96
Ratings
typ
25
80
–80
max
35
5
75
Unit
mA
µA
µA
µA
V
V
V
1V
0.4 V
0.5 V
5 µA
µA
96 µA
–64 µA
No. 5811-4/27

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LC78624E 전자부품, 판매, 대치품
LC78624E
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol
DEFI
TAI
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
TEST2
CLV+
CLV
V/P
HFL
TES
TOFF
TGL
JP+
JP
PCK
FSEQ
VDD
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
C2F
DOUT
TEST3
TEST4
TEST6
TEST7
LRSY
CK2
ROMXA
SRDT
DQSY
SCLK
TEST8
XVDD
XOUT
XIN
XVSS
SBSY
EFLG
PW
SFSY
I/O Function
I Defect detection signal (DEF) input. (Must be connected to 0 V when unused.)
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
O External VCO control phase comparator output
PLL pins
AI
Internal VCO ground. Must be connected to 0 V.
PDO output current adjustment resistor connection
– Internal VCO power supply
AI VCO frequency range adjustment
– Digital system ground. Must be connected to 0 V.
O
Slice level control
I
EFM signal output
EFM signal input
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
O Disc motor control output.
O Three-value output is also possible when specified by microcontroller command.
Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level
O during phase control.
I Track detection signal input. This is a Schmitt input.
I Tracking error signal input. This is a Schmitt input.
O Tracking off output
O Tracking gain switching output. Increase the gain when low.
O Track jump control output.
O Three-value output is also possible when specified by microcontroller command.
O EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.
Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM
O signal and the internally generated synchronization signal agree.
– Digital system power supply.
I/O General-purpose I/O pin 1
I/O General-purpose I/O pin 2
I/O General-purpose I/O pin 3
I/O General-purpose I/O pin 4
Controlled by serial data commands from the microcontroller. Any of these that are unused
must be either set up as input ports and connected to 0 V, or set up as output ports and
left open.
I/O General-purpose I/O pin 5
O De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk.
O C2 flag output
O Digital output. (EIAJ format)
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
I Test input. A pull-down resistor is built in. Must be connected to 0 V.
O Test output
O L/R clock output
O ROMXA output
O
Bit clock output
Interpolated data output, not ROM output
O Text data output
O Text readout enable output
I Text shift clock input
O Test output
– Crystal oscillator power supply.
O
Connections for a 16.9344 crystal oscillator element
I
– Crystal oscillator ground. Must be connected to 0 V.
O Subcode block synchronization signal output
O C1, C2, single and double error correction monitor pin
O Subcode P, Q, R, S, T, U, V and W output
O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.
Continued on next page.
No. 5811-7/27

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부품번호상세설명 및 기능제조사
LC78624E

Compact Disc Player DSP

Sanyo Semicon Device
Sanyo Semicon Device

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