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LC78625E 데이터시트 PDF
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PDF 형식의 LC78625E 자료 제공
| 부품번호 | LC78625E 기능 |
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| 기능 | Compact Disc Player DSP | ||
| 제조업체 | Sanyo Semicon Device | ||
| 로고 |  |
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전체 30 페이지수
Ordering number : EN5502
CMOS LSI
LC78625E
Compact Disc Player DSP
Overview
The LC78625E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players, laser discs, CD-V, CD-I and related products. The
LC78625E provides several types of signal processing,
including demodulation of the optical pickup EFM signal,
de-interleaving, error detection and correction, and digital
filters that can help reduce the cost of CD player units. It
also processes a rich set of servo system commands sent
from the control microprocessor. It also incorporates an
EFM-PLL circuit and a one-bit D/A converter.
This LSI is an improved version of the LC78620E. In
addition to supporting low-voltage operation, on/off
control of the de-emphasis function and use of the
bilingual function have been enabled in certain additional
modes.
Functions
• The LC78625E takes an HF signal as input, digitizes
(slices) that signal at a precise level, converts that signal
to an EFM signal, and generates a PLL clock with an
average frequency of 4.3218 MHz by comparing the
phases of that signal and an internal VCO.
• A precise reference clock and the necessary internal
timings are generated using an external 16.9344 MHz
crystal oscillator.
• Disc motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection, and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output (LSB first) to a microprocessor
over the serial interface after performing a CRC error
check
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disc rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78625E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a quadruple interpolation scheme. The
output value converges to the muting level when four or
more consecutive C2 flags occur.
Package Dimensions
unit: mm
3174-QFP80E
[LC78625E]
SANYO: QFP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5502-1/35
 
Continued from preceding page.
Parameter
Command transfer time
Subcode Q read enable time
Subcode read cycle
Subcode read enable time
Port input data setup time
Port input data hold time
Port input clock setup time
Port output data delay time
Input level
Operating frequency range
Crystal oscillator frequency
LC78625E
Symbol
Conditions
tRWC
tSQE
tSC
tSE
tPSU
tPHD
tRCQ
tPDD
VIN (1)
VIN (2)
fOP (1)
fX
RWC : Figure 1
WRQ: Figure 2, with no RWC signal
SFSY : Figure 3
SFSY : Figure 3
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 4
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 4
CQCK, RWC : Figure 4
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 5
EFMIN
XIN : Capacitor coupled input
EFMIN
XIN, XOUT : In 16M mode
min
1000
400
400
Ratings
typ
11.2
136
400
100
1.0
1.0
16.9344
Unit
max
ns
ms
µs
ns
ns
1200
10
ns
ns
ns
Vp-p
Vp-p
MHz
MHz
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Symbol
Conditions
Ratings
min typ max
Current drain
IDD
30
Input high-level current
IIH (1)
DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK : VIN = 5 V
TAI, TEST1 to TEST5, DEMO, CS :
IIH (2) VIN = VDD = 5.5 V
25
Input low-level current
IIL
VOH (1)
DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK, TAI, TEST1 to
TEST5, DEMO, CS : VIN = 0 V
EFMO, EFMO, CLV+, CLV–, V/P, FOCS,
PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–,
EMPH, EFLG, FSX : IOH = –1 mA
–5
4
Output high-level voltage
VOH (2)
MUTEL, MUTER, LRCKO, DFORO, DFOLO,
DACKO, TST10, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, LRSY, CK2,
ROMXA, C2F, SBSY, PW, SFSY, WRQ,
SQOUT, TST11, 16M, 4.2M, CONT :
IOH = –0.5 mA
4
VOH (3) LASER : IOH = –1 mA
4.6
VOH (4) DOUT : IOH = –12 mA
4.5
VOH (5)
VOL (1)
LCHP, RCHP, LCHN, RCHN : IOH = –1 mA
EFMO, EFMO, CLV+, CLV–, V/P, FOCS,
PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–,
EMPH, EFLG, FSX : IOL = 1 mA
3.0
Output low-level voltage
VOL (2)
MUTEL, MUTER, LRCKO, DFORO, DFOLO,
DACKO, TST10, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, LRSY, CK2,
ROMXA, C2F, SBSY, PW, SFSY, WRQ,
SQOUT, TST11, 16M, 4.2M, CONT, LASER :
IOL = 2 mA
VOL (3) DOUT : IOL = 12 mA
VOL (4) FST : IOL = 5 mA
Output off leakage current
VOL (5)
IOFF (1)
IOFF (2)
LCHP, RCHP, LCHN, RCHN : IOL = 1 mA
PDO, CLV+, CLV–, JP+, JP–, FST :
VOUT = 5 V
PDO, CLV+, CLV–, JP+, JP– : VOUT = 0 V
0.5
–5
Charge pump output current
IPDOH
IPDOL
PDO : RISET = 68 kΩ
PDO : RISET = 68 kΩ
100
–150
125
–125
Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 kΩ ±5.0% tolerance resistor.
45
5
75
4.5
1
0.4
0.5
0.75
2.0
5
150
–100
Unit
mA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
No. 5502-4/35
4페이지 
LC78625E
One-Bit D/A Converter Output Block Reference Circuit
No. 5502-7/35
7페이지 | |||
| 구 성 | 총 30 페이지수 | ||
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관련 데이터시트
| 부품번호 | 상세설명 및 기능 | 제조사 |
| LC78625 | Compact Disc Player DSP | Sanyo Semicon Device |
| LC78625E | Compact Disc Player DSP | Sanyo Semicon Device |
| DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |