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LC78628 데이터시트 PDF
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PDF 형식의 LC78628 자료 제공
| 부품번호 | LC78628 기능 |
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| 기능 | Compact Disc Player DSP with Built-in HDCD Decoder | ||
| 제조업체 | Sanyo Semicon Device | ||
| 로고 |  |
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전체 30 페이지수
Ordering number : ENN6329
CMOS IC
LC78628E
Compact Disc Player DSP with Built-in HDCD Decoder
®
Overview
The LC78628E CMOS IC implements signal processing
and servo control for compact disc players, laser disc
players, CD-V, CD-I, and similar products. It provides
functions for demodulation of the EFM signal from the
optical pickup, deinterleaving, error detection and
correction, and processing servo system commands issued
by the system microprocessor. In addition to this basic CD
functionality, it also provides HDCD (High Definition
Compatible Digital) decoding functions and CD text
functions. It also includes a built-in EFM PLL circuit.
Functions
• Full decoding and playback for discs encoded with the
HDCD technique developed by Pacific Microsonics,
Inc.
• Slices the high-frequency input signal at an accurate
level, converts it into the EFM signal, and generates a
PLL clock with an average frequency of 4.3218 MHz
performing a phase comparison with an internal VCO.
• Accurately generates a reference clock signal and all
necessary internal timings using an external 16.9344-
MHz crystal.
• Controls the disc motor speed using a frame phase
difference signal created based on the reproduced clock
signal and the reference clock.
• Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
• Demodulates the EFM signal, converting it to 8-bit
symbol data.
• After applying a CRC check to the subcode Q signal,
outputs that data to the control microprocessor using
serial data transfer.
Package Dimensions
Continued on next page.
unit: mm
3174-QIP80E
0.8 0.8
64
65
[LC78628E]
23.2
20.0
0.35
1.6
41
40
0.15
80
1
25
24
2.7
21.6 0.8
SANYO: QIP80E
®
HDCD® (High Definition Compatible Digital®) is a registered trademark of Pacific Microsonics, Inc.
in the US and other countries.
A license from Pacific Microsonics, Inc. is required to use this product.
Sanyo Electric Co., Ltd. has acquired license for the use of HDCD technology from Pacific Microsonics, Inc.
The following patents apply to the design of this product:
USA: 5479168, 5638074, 5640161, 5808574, 5838274, 5854600, and 5872531.
Australia: 669114
Other patents have also been applied for.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32400RM (OT) No. 6329-1/40
 
LC78628E
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min typ max
Input level
Data setup time
Data hold time
High-level clock pulse width
Low-level clock pulse width
Data read access time
Command output time
Subcode Q readout enable time
Port input setup time
Port input hold time
Port input clock setup time
Port output data delay time
Text readout period
DQSY pulse width
SCLK high-level clock pulse width
SCLK low-level clock pulse width
SCLK clock delay time
Text data delay time
Reset time
Operating frequency range
Crystal oscillator frequency
VIN1
VIN2
tSU
tHD
tWH
tWL
tRAC
tRWC
tSQE
tCSU
tCHD
tRCQ
tCDD
tCW
tW
tWTH
tWTL
tD1
tD2
tD3
tRES
fOP
fX
EFMIN: Slice level control
XIN: Capacitor coupled input
COIN, RWC, *: See figure 1.
COIN, RWC, *: See figure 1.
CQCK, *: See figures 1 and 2.
CQCK, *: See figures 1 and 2.
SQOUT: See figures 2.
RWC, *: See figures 1.
WRQ, normal speed: See figures 2, RWC = VIL1
P0 to P4, RWC: See figures 3.
P0 to P4, RWC: See figures 3.
CQCK, RWC, *: See figures 3.
P0 to P4, RWC: See figure 4.
DQSY, normal speed: See figure 5.
DQSY, normal speed: See figure 5.
SCLK: See figure 5.
SCLK: See figure 5.
SCLK: See figure 5.
SRDT: See figure 5.
SRDT: See figure 5.
RES
EFMIN
XIN, XOUT
1.0
1.0
400
400
400
400
0
1000
400
400
100
1.5
60
100
100
100
11.2
3.3
136
400
16.9344
400
1200
3.7
150
50
50
10
Notes: The same voltage must be applied to all 5 V system power supply pins.
* When used in conjunction with an ASP that provides a command interface, the stricter ratings of the ASP shall be given priority.
Unit
Vp-p
Vp-p
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ms
µs
ns
ns
ns
ns
ns
ns
MHz
MHz
No. 6329-4/40
4페이지 
LC78628E
CQCK
RWC
P0 to P4
HDCD
GAIN
SQOUT
tRCQ
tCSU tCHD
tRA
P0 P1
P2 P3
P4 HDCD GAIN
Figure 3 General-Purpose Port Input Timing
A12799
4.2M
RWC
P0 to P4
DQSY
SCLK
SRDT
tCDD
Figure 4 General-Purpose Port Output Timing
tW
tWTL tWTL
tD1
tCW
tD2
Flag D0
tD3
D1
D2
D127
Figure 5 Text Data Output Timing
A12800
A12801
No. 6329-7/40
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