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LC78630 데이터시트 PDF




Sanyo Semicon Device에서 제조한 전자 부품 LC78630은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 LC78630 기능
기능 Compact Disk Player DSP
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LC78630 데이터시트, 핀배열, 회로
Ordering number : EN 5121B
CMOS LSI
LC78630E
Compact Disk Player DSP
Overview
The LC78630E is a CD-DA signal-processing LSI for use
in video CD player systems. The LC78630E incorporates
signal-processing circuits for demodulating and de-
interleaving the EFM signal from the optical pickup, error
detection and correction, and digital filtering. It also
includes a 1-bit D/A converter and executes commands
sent from a system control microprocessor.
Features
• Built-in PLL for EFM signal synchronization (a hybrid
analog-digital PLL that supports 4× playback)
• Built-in PLL for variable pitch playback (±13%)
• 18KB RAM on chip
• Error detection and correction (corrects two errors in C1
and four errors in C2)
• Frame jitter margin: ±8 frames
• Frame synchronization signal detection, protection, and
insertion
• Dual interpolation adopted in the interpolation circuit.
• EFM data demodulation
• Subcode demodulation
• Zero-cross muting adopted
• Servo command interface
• 2fs digital filter
• Digital de-emphasis
• Built-in independent left- and right-channel digital
attenuators (239 attenuation steps)
• Left/right swap function
• Built-in 1-bit D/A converter (third-order ∆∑ noise
shaper, PWM output)
• Built-in digital output circuit
• CLV servo
• Arbitrary track jumping (of up to 255 tracks)
• Variable sled voltage (four levels)
• Built-in oscillator circuit using an external 16.9344 MHz
or 33.8688 MHz (for 4× playback) element
• Supply voltage: 3.6 to 5.5 V (4.5 to 5.5 V for 4×
playback mode)
• Six extended I/O ports and 2 extended output ports
Package Dimensions
unit: mm
3174-QFP80E
[LC78630E]
SANYO: QIP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
83097HA (OT)/D3095HA (OT)/60595HA (OT) No. 5121-1/33




LC78630 pdf, 반도체, 판매, 대치품
LC78630E
Continued from preceding page.
Parameter
Symbol
Conditions
High-level clock pulse width
tWH SBCK, CQCK: Figures 1, 2, 3, and 4
Low-level clock pulse width
tWL SBCK, CQCK: Figures 1, 2, 3, and 4
Data read access time
tRAC
SQOUT, PW: Figures 2, 3, and 4
Command transfer time
tRWC RWC: Figures 1 and 4
Subcode Q read enable time
tSQE
WRQ: Figure 2, with no RWC signal
Subcode read cycle
tSC SFSY: Figure 3
Subcode read enable
tSE SFSY: Figure 3
Port output delay time
tPD CONT1, CONT2, P0 to P5: Figure 5
Input level
VEI EFMI
VXI XIN: Capacitance coupled input
Note: Due to the structure of this IC, the identical voltage must be applied to all power-supply pins.
min
400
400
0
1000
400
1.0
1.0
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Current drain
Input high-level current
Input low-level current
Output high-level voltage
Output low-level voltage
Output off leakage current
Charge pump output current
Sled output voltage
Symbol
IDD
IIH1
IIH2
IIL
VOH1
VOH2
VOH3
VOH4
VOH5
VOL1
VOL2
VOL3
VOL4
VOL5
IOFF1
IOFF2
IPDOH
IPDOL
VSLD1
VSLD2
VSLD3
VSLD4
Conditions
EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES,
DEFI: VIN = 5 V
TAI, TEST1 to TEST5, CS: VIN = 5 V
TAI, EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES,
TEST1 to TEST5, CS, DEFI: VIN = 0 V
EFMO, CLV+, CLV, V/P, PCK, FSEQ, TOFF, TGL,
THLD, JP+, JP, EMPH, EFLG, FSX: IOH = –1 mA
MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK,
P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M,
CONT1, CONT2: IOH = –0.5 mA
VPDO: IOH = –1 mA
DOUT: IOH = –12 mA
LCHP, RCHP, LCHN, RCHN: IOH = –1 mA
EFMO, CLV+, CLV, V/P, PCK, FSEQ, TOFF, TGL,
THLD, JP+, JP, EMPH, EFLG, FSX: IOL = 1 mA
MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK,
P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M,
CONT1, CONT2: IOL = 2 mA
VPDO: IOL = 1 mA
DOUT: IOL = 12 mA
LCHP, RCHP, LCHN, RCHN: IOL = 1 mA
PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN,
P2, P3/DFLR, P4, P5: VOUT = 5 V
PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN,
P2, P3/DFLR, P4, P5: VOUT = 0 V
PDO1, PDO2: RISET = 68 k
PDO1, PDO2: RISET = 68 k
min
25
–5
4
4
4.5
4.5
3.0
0.5
–5
–96
64
1.0
2.25
3.5
4.75
typ
11.2
136
typ
30
–80
80
1.25
2.5
3.75
max
400
1200
Unit
ns
ns
ns
ns
ms
µs
ns
ns
Vp-p
Vp-p
max Unit
mA
5 µA
75 µA
µA
V
V
V
V
4.5 V
1V
0.4
0.5
0.5
2.0
5
–64
96
1.5
2.75
4.0
V
V
V
V
µA
µA
µA
µA
V
V
V
V
No. 5121-4/33

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LC78630 전자부품, 판매, 대치품
LC78630E
One-Bit D/A Converter Output Block Reference Circuit
No. 5121-7/33

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