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LC78631 데이터시트 PDF
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PDF 형식의 LC78631 자료 제공
| 부품번호 | LC78631 기능 |
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| 기능 | Compact Disk Player DSP | ||
| 제조업체 | Sanyo Semicon Device | ||
| 로고 |  |
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Ordering number : EN 5342
CMOS LSI
LC78631E
Compact Disk Player DSP
Overview
The LC78631E is a compact disc D/A signal-processing
LSI for CD-ROM drives that provides a variable clock
error correction (VCEC) mode. The LC78631E
demodulates the EFM signal from the optical pickup and
performs de-interleaving, error detection, error correction,
digital filtering, and other processing. The LC78631E
includes an on-chip 1-bit D/A converter, and executes
commands sent from a control microprocessor.
Features
• VCEC support
• Built-in PLL circuit for EFM detection (supports 4×
playback)
• Built-in PLL for variable pitch playback (±13%)
• 18KB RAM on chip
• Error detection and correction (corrects two errors in C1
and four errors in C2)
• Frame jitter margin: ±8 frames
• Frame synchronization signal detection, protection, and
insertion
• Dual interpolation adopted in the interpolation circuit.
• EFM data demodulation
• Subcode demodulation
• Zero-cross muting adopted
• Servo command interface
• 2fs digital filter
• Digital de-emphasis
• Built-in independent left- and right-channel digital
attenuators (239 attenuation steps)
• Supports the bilingual function
• Left/right swap function
• Built-in 1-bit D/A converter (third-order ∆∑ noise
shaper, PWM output)
• Built-in digital output circuit
• CLV servo
• Arbitrary track jumping (of up to 255 tracks)
• Variable sled voltage (four levels)
• Six extended I/O ports and 2 extended output ports
• Built-in oscillator circuit using an external 16.9344 MHz
or 33.8688 MHz (for 4× playback) element
• Supply voltage: 3.6 to 5.5 V (4.75 to 5.5 V for 4×
playback mode)
Package Dimensions
unit: mm
3174-QFP80E
[LC78631E]
SANYO: QFP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT) No. 5342-1/34
 
LC78631E
Continued from preceding page.
Parameter
High-level clock pulse width
Low-level clock pulse width
Data read access time
Command transfer time
Subcode Q read enable time
Subcode read cycle
Subcode read enable
Port output delay time
Input level
Symbol
tWH
tWL
tRAC
tRWC
tSQE
tSC
tSE
tPD
VEI
VXI
Conditions
SBCK, CQCK: Figures 1, 2, 3, and 4
SBCK, CQCK: Figures 1, 2, 3, and 4
SQOUT, PW: Figures 2, 3, and 4
RWC: Figures 1 and 4
WRQ: Figure 2, with no RWC signal
SFSY: Figure 3
SFSY: Figure 3
CONT1, CONT2, P0 to P5: Figure 5
EFMI
XIN: Capacitance coupled input
Note: Due to the structure of this IC, the identical voltage must be applied to all power-supply pins.
min
400
400
0
1000
400
1.0
1.0
typ
11.2
136
max
400
1200
Unit
ns
ns
ns
ns
ms
µs
ns
ns
Vp-p
Vp-p
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Current drain
Input high-level current
Input low-level current
Output high-level voltage
Output low-level voltage
Output off leakage current
Charge pump output current
Sled output voltage
Symbol
IDD
IIH1
IIH2
IIL
VOH1
VOH2
VOH3
VOH4
VOH5
VOL1
VOL2
VOL3
VOL4
VOL5
IOFF1
IOFF2
IPDOH
IPDOL
VSLD1
VSLD2
VSLD3
VSLD4
Conditions
Normal-speed playback
EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES,
DEFI: VIN = 5 V
TAI, TEST1 to TEST5, CS: VIN = 5 V
TAI, EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES,
TEST1 to TEST5, CS, DEFI: VIN = 0 V
EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL,
THLD, JP+, JP–, EMPH, EFLG, FSX, FAST:
IOH = –1 mA
MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK,
P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M,
CONT1, CONT2: IOH = –0.5 mA
VPDO: IOH = –1 mA
DOUT: IOH = –12 mA
LCHP, RCHP, LCHN, RCHN: IOH = –1 mA
EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL,
THLD, JP+, JP–, EMPH, EFLG, FSX, FAST:
IOL = 1 mA
MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK,
P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA,
C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M,
CONT1, CONT2: IOL = 2 mA
VPDO: IOL = 1 mA
DOUT: IOL = 12 mA
LCHP, RCHP, LCHN, RCHN: IOL = 1 mA
PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN,
P2, P3/DFLR, P4, P5: VOUT = 5 V
PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN,
P2, P3/DFLR, P4, P5: VOUT = 0 V
PDO1, PDO2: RISET = 68 kΩ
PDO1, PDO2: RISET = 68 kΩ
min
25
–5
4
4
4.5
4.5
3.0
0.5
–5
–96
64
1.0
2.25
3.5
4.75
typ max Unit
30 mA
5 µA
75 µA
µA
V
V
V
V
4.5 V
1V
–80
80
1.25
2.5
3.75
0.4
0.5
0.5
2.0
5
–64
96
1.5
2.75
4.0
V
V
V
V
µA
µA
µA
µA
V
V
V
V
No. 5342-4/34
4페이지 
LC78631E
One-Bit D/A Converter Output Block Reference Circuit
No. 5342-7/34
7페이지 | |||
| 구 성 | 총 30 페이지수 | ||
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관련 데이터시트
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| DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |