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PDF UC3843T Data sheet ( Hoja de datos )
| Número de pieza | UC3843T | |
| Descripción | (UC3842T - UC3845T) HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UC3843T (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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www.DataSheet4U.com
UC3842T UC3843T
® UC3844T UC3845T
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
. TRIMMED OSCILLATOR FOR PRECISE FRE-
QUENCY CONTROL
. OSCILLATOR FREQUENCY GUARANTEED
AT 250kHz
. CURRENT MODE OPERATION TO 500kHz
. AUTOMATIC FEED FORWARD COMPENSA-
TION
. LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
. INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
. HIGH CURRENT TOTEM POLE OUTPUT
. UNDERVOLTAGE LOCKOUT WITH HYSTER-
ESIS
. LOW START-UP AND OPERATING CURRENT
DESCRIPTION
The UC384XT family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally imple-
mented circuits include a trimmed oscillator for pre-
cise DUTY CYCLE CONTROL under voltage lock-
out featuring start-up current less than 0.5mA, a pre-
cision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
Minidip
SO8
comparator which also provides current limit control,
and a totem pole output stage designed to source
or sink high peak current. The output stage, suitable
for driving N-Channel MOSFETs, is low in the off-
state.
Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC3842T and UC3844T have
UVLO thresholds of 16V (on) and 10V (off), ideally
suited to off-line applications The corresponding
thresholds for the UC3843T and UC3845T are 8.5 V
and 7.9 V. The UC3842T and UC3843T can operate
to duty cycles approaching 100%. A range of zero to
< 50 % is obtained by the UC3844T and UC3845T by
the addition of an internal toggle flip flop which blanks
the output off every other clock cycle.
BLOCK DIAGRAM (toggle flip flop used only in UC3844T and UC3845T)
7
Vi
5
GROUND
4
RT/CT
VFB
COMP
CURRENT
SENSE
2
1
3
34V UVLO
S/R
5V
REF
2.50V
VREF GOOD
LOGIC
INTERNAL
BIAS
OSC
ERROR AMP.
+
-
2R
R
T
S
R
1V
CURRENT
SENSE
COMPARATOR
PWM
LATCH
8 VREF
5V 50mA
6
OUTPUT
D95IN331
September 2001
1/15
1 page  
Figure 1: Open Loop Test Circuit.
www.DataSheet4U.com
U3842T - UC3843T - UC3844T - UC3845T
4.7KΩ
ERROR AMP.
ADJUST
4.7KΩ
2N2222
100KΩ
1KΩ
ISENSE
ADJUST
5KΩ
RT
COMP
VFB
ISENSE
RT/CT
VREF
8
1
2
D.U.T.
3
4
7
6
5
0.1µF
Vi
OUTPUT
0.1µF
GROUND
D95IN343
CT
A
1W
1KΩ
VREF
Vi
OUTPUT
GROUND
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pin 5 in a single point ground. The transistor and
5 KΩ potentiometer are used to sample the oscillator
waveform and apply an adjustable ramp to pin 3.
Figure 2: Timing Resistor vs. Oscillator Fre-
quency
RT
(KΩ)
50
20
CT=5nF
10
D95IN333
C
T=200pF
C
CT
T=500pF
=1nF
CT=100pF
5
2
Vi=15V
TA=25˚C
1
0.8
10K
20K
CT=10nF
30K 50K
CT=2nF
100K 200K 300K 500K fOSC(KHz)
Figure 3: Output Dead-Time vs. Oscillator Fre-
quency
D95IN334
%
50
30
20
10
5
3
2
1
10K
CT=1nF
CT=500pF
CT=200pF
CT=2nF
CT=5nF
CT=10nF
CT=100pF
Vi=15V
TA=25˚C
20K 30K 50K
100K 200K 300K 500K fOSC(KHz)
5/15
5 Page 
Figure 22: External Clock Synchronization.
www.DataSheet4U.com
U3842T - UC3843T - UC3844T - UC3845T
EXTERNAL
SYNC INPUT 0.01µF
VREF
8
RT
4
CT
2
47Ω
1
R
R
+
+
-
EA
BIAS
OSC
2R
R
5
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
D95IN352
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
VREF
RA
8
RB 5K
6
+
5
-
5K
+
2
-
C 5K
1
4
R
Q
S
NE555
1.44
f=
(RA + 2RB)C
Dmax =
RB
RA + 2RB
3
7
8
R
BIAS
R
4
OSC
+
+
2
-
EA
1
2R
R
5
TO ADDITIONAL
UC384XT
D99IN1060
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet UC3843T.PDF ] | |
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