LC78711 Datasheet PDF - Sanyo Semicon Device
| Part Number | LC78711 | |
| Description | Graphics Display Processor | |
| Manufacturers | Sanyo Semicon Device | |
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Ordering number : EN5476
CMOS LSI
LC78711E
Graphics Display Processor
Overview
The LC78711E is a CMOS LSI that provides graphics
display drawing functions. In addition to implementing
graphics display for NTSC and PAL signals, it provides
two 32 × 32-dot sprite display patterns and can easily
implement a wide range of displays.
Features
• Two-chip structure consisting of this LSI, the
LC78711E, and an external 64-K × 4-bit RAM. (An
RGB encoder is built in.)
• Graphics drawing controlled by a microprocessor over a
serial interface.
• Includes two crystal oscillator systems, one for NTSC
and one for PAL, and these system can be easily
switched using the provided control pin.
The standard clocks and all necessary internal timings
can be generated by connecting two crystals, a
14.31818-MHz crystal for NTSC, and a 17.734476-MHz
crystal for PAL.
• Two 32 × 32-dot sprite patterns provided. Up to two
sprites can be displayed, either two different types or the
same pattern in two different locations.
• 16 colors from a palette of 4096 colors can be displayed
in graphics screens, and seven colors can be displayed in
sprite patterns.
• Y/C signal outputs (two 8-bit D/A converter outputs)
• Supports the superimpose function, and provides a
timing signal output.
• Provides a color bar signal output function.
• Adopts an 8-bit serial data input format for the external
control input.
Package Dimensions
unit: mm
3159-QFP64E
[LC78711E]
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
63096HA (OT) No. 5476-1/43
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LC78711E
Basic Specifications
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Pin
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
DVDD1
CE
DO
DI
CL
PSC1
PSC2
WAIT
INT
TEST7
DVSS1
WE
RAS
A0
A1
A2
A3
A4
A5
A6
A7
DB0
CAS
DB1
OE
DB2
DB3
CB
TEST8
AVSS1
AVDD1
VIDEO1
BIAS
VIDEO2
BFP
Pin type
Test input
Test input
Test output
Test input
Test input
Test input
Power supply (+5 V)
Enable input
Data output
Data input
Clock input
Monitor 1 output
Monitor 2 output
Wait signal output
Wait signal output
Test input
Ground
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM output
DRAM input and output
DRAM output
DRAM input and output
DRAM output
DRAM input and output
DRAM input and output
Color bar selection
Test output
Ground
Power supply (+5 V)
Video signal (Y) output
Capacitor connection
Video signal (C) output
Burst flag signal output
I/O
I
I
O
I
I
I
—
I
O
I
I
O
O
O
O
I
—
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
I/O
I
O
—
—
O
O
O
O
42
LINE
Line count selection
I
43
FSCIN
Clock input
I
44
VSYNC
Vertical synchronization output
O
45
TEST9
Test input
I
46 YS Superimpose output
O
47
CSYNC
Composite synchronization output O
48
4FSC2
Clock input
I
49
TEST10
Test output
50
TEST11
Test output
O
O
Polarity
Positive
Positive
Positive
Positive
Positive
Positive
—
Positive
Positive
Positive
Positive
Positive
Positive
Negative
Negative
Positive
—
Negative
Negative
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Positive
Negative
Positive
Negative
Positive
Positive
Positive
Positive
—
—
—
—
—
Positive
—
Positive
Negative
Positive
Negative
Negative
Positive
Positive
Positive
Pin function
Test input. Must be connected to ground during normal operation.
Test input. Must be connected to ground during normal operation.
Test output
Test input. Must be connected to ground during normal operation.
Test input. Must be connected to ground during normal operation.
Test input. Must be connected to ground during normal operation.
Digital system power supply
Serial I/O data control input
Serial data output
Serial data input
Serial data I/O clock input
Serial input monitor signal output
Command monitor signal output
Serial input wait signal output (for use with bit maps)
Serial input wait signal output (for use with the sprite function)
Test input. Must be connected to ground during normal operation.
Digital system ground
DRAM write enable signal output
DRAM row address strobe signal output
DRAM address (A0) output (Functions as an input in test mode.)
DRAM address (A1) output (Functions as an input in test mode.)
DRAM address (A2) output (Functions as an input in test mode.)
DRAM address (A3) output (Functions as an input in test mode.)
DRAM address (A4) output (Functions as an input in test mode.)
DRAM address (A5) output (Functions as an input in test mode.)
DRAM address (A6) output (Functions as an input in test mode.)
DRAM address (A7) output (Functions as an input in test mode.)
DRAM data (D0) input and output
DRAM column address strobe signal output
DRAM data (D1) input and output
DRAM read enable signal output
DRAM data (D2) input and output
DRAM data (D3) input and output
Low: normal mode, high: color bar output
(A pull-down resistor is built in.)
Test output
Analog system ground
Analog system power supply
Video (luminance) signal (analog) output (D/A converter output)
Connections for a ripple exclusion capacitor
Video (chrominance) signal (analog) output (D/A converter output)
Burst signal output timing flag output
Line count selection
NTSC mode - Low: 263H, high: 262H
PAL mode - Low: 314H, high: 312H
Superimpose subcarrier clock input (A feedback resistor is built in.)
Vertical synchronizing signal output
Test input. Must be connected to ground during normal operation.
(A pull-down resistor is built in.)
Superimpose control output
Composite synchronizing signal output
External clock input for the superimpose function
(A feedback resistor is built in.)
Test output
Test output
Continued on next page.
No. 5476-5/43
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| Information | Total 30 Pages | |
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