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Ordering number : EN5521

CMOS LSI

LC7874E

CD Graphics Decorder

Overview

The LC7874E is a CMOS LSI that provides the signal

processing needed for compact disc graphics (CD-G) on a

single chip. The LC7874E accepts subcode R to W

signals output from a CD player DSP LC786X Series,

LC7862XE Series, or LC7863XE Series device, and

performs de-interleaving, error detection and correction,

graphic instruction processing, and image processing.

Features

• A CD-G decoder can be configured using a three-chip

combination of this LSI—the LC7874E—with external

RAM (64K × 4 bits) and an LC78010E digital RGB

encoder.

• Performs insertion and protection of CD subcode R to

W sync signals and detection of R to W signal de-

interleave error signals.

• Has two crystal oscillators, for NTSC and PAL, with

simple switchover by means of a control pin.

Connecting a crystal resonator of 14.31818 MHz for

NTSC and 17.734476 MHz for PAL enables the

standard clock and other necessary timings to be

generated internally.

• Performs CD graphics instruction processing and

drawing functions, and controls image display.

• Has microcomputer interface functions, allowing set

upgrading.

• Provides superimposition support.

• Has a color bar signal output function.

• DRAM interface and RGB output and sync signal output

are 3-state outputs.

Package Dimensions

unit: mm

3159-QFP64E

[LC7874E]

SANYO: QIP64E

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus

addresses are controlled by SANYO.

Specifications

Electrical Characteristics at Ta = –30°C to +85°C

Parameter

Power supply voltage

Input voltage

Output voltage

Allowable power dissipation

Operating temperature

Storage temperature

Symbol

VDD

VIN

VOUT

Pd max

Topr

Tstg

Conditions

Ratings

VDD

S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to 3,

VSS – 0.3 to VSS + 7.0

CB, CE1, CE2, CE3, LINE, HRESET, VRESET, INIT,

RESET, N/P, SON, XIN1, XIN2

VSS – 0.3 to VDD + 0.3

SBCK, DO, CDGM, WE, RAS, A0 to 7, DB0 to 3, CAS, OE,

ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, HSYNC, CSYNC,

BLANK, YS, 4FSCO, EFLG, FSCO, XOUT1, XOUT2

VSS – 0.3 to VDD +0 .3

Ta = 25°C

500

–30 to +85

–40 to +125

Unit

V

V

V

mW

°C

°C

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

13097HA(OT) No. 5521-1/22

LC7874E

Timing Characteristics (DRAM Access Timing) at Ta = 25°C, VDD = 5 V

Parameter

Random read/write cycle time

Page mode cycle time

RAS precharge time

RAS pulse width

RAS pulse width (page mode)

RAS hold time

CAS hold time

CAS pulse width

CAS precharge time

CAS precharge time

Row address setup time

Row address hold time

Column address setup time

Column address hold time

Read command setup time

Read command hold time

Read command hold time

Write command setup time

Write command hold time

Write command pulse width

Write data setup time

Write data hold time

CAS setup time

CAS hold time

RAS precharge CAS active time

Read data setup time

Read data hold time

Refresh time

Symbol

Conditions

tRC

tPC

tRP

tRAS

tRASP

tRSH

tCSH

tCAS

tCPN

tCP

tASR

tRAH

tASC

tCAH

tRCS

tRCH

tRRH

tWCS

tWCH

tWP

tDS

tDH

tCSR

tCHR

tRPC

tRDS

tRDH

tREF

(In page mode)

(Referenced to CAS )

(Referenced toRAS)

(CAS before RAS)

(CAS before RAS)

min

250

130

100

120

Ratings

typ

60

120

60

50

50

100

50

0

50

150

120

120

100

50

150

100

100

50

50

50

20

10

max

18000

3.5

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

No. 5521-4/22

DRAM Page Mode Read Cycle

LC7874E

No. 5521-7/22

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