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Ordering number : EN*4250C

Preliminaly

CMOS LSI

LC78816MB, 78816MC

16-Bit D/A Converter for Use in

Digital Audio Products

Overview

The LC78816MB and 78816MC are 16-bit CMOS D/A

converters for use in digital audio products. They employ

a dynamic level shift conversion technique that combines

a resistor string (for the upper 9 bits), PWM (for the

middle 3 bits), and level shifting (for the lower 4 bits).

Features

• Two’s complement data format

• Two D/A converter channels built in (in-phase outputs)

• Maximum conversion frequency of 400 kHz (support for

8 times oversampling)

• Built-in output op amps

• No deglitching circuit required

• Si gate CMOS process (low power consumption)

• 5 V single-voltage power supply

• Low voltage (3.5 V) operation possible

Package Dimensions

unit: mm

3036B-MFP20

[LC78816MB, 78816MC]

SANYO: DIP20

Specifications

Absolute Maximum Ratings at Ta = 25°C

Parameter

Maximum power supply voltage

Input voltage

Output voltage

Operating temperature

Storage temperature

Symbol

VDD max

VIN

VOUT

Topr

Tstg

Allowable Operating Ranges

Parameter

Power supply voltage

Reference voltage high

Reference voltage low

Operating temperature

Symbol

VDD

VrefH

VrefL

Topr

Conditions

Ratings

–0.3 to +7.0

–0.3 to VDD + 0.3

–0.3 to VDD + 0.3

–30 to +75

–40 to +125

Unit

V

V

V

°C

°C

Conditions

min

3.5

VDD – 0.3

0

–30

Ratings

typ

5.0

max

5.5

VDD

0.3

+75

Unit

V

V

V

°C

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

63096HA (OT)/D1694TH(OT)/61893JN No. 4250-1/11

Block Diagram

LC78816MB, 78816MC

Pin Functions

Pin No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Pin Name

CH1OUT

REFH

VrefH

AVDD

LRCK/WCLK

DATAL

DATAR

BCLK

SYSCLK

DVDD

TSTOUT

FSEL

MODE1

MODE2

DGND

REFL

AGND

VrefL

NC

CH2OUT

Function and Operational Description

Channel 1 output pin (left channel)

Reference voltage high level pin

Normally connected to AGND through a capacitor.

Reference voltage high level input pin

Analog system power supply voltage pin

LR clock and word clock input pin

Used to generate the internal signal that latches the digital audio data (DATAL and DATAR).

Digital audio data input pin

Data is input from the MSB bit serially.

When FSEL is low, channel 1 data is input.

When FSEL is high, channel 1 and channel 2 data are input using time division.

Digital audio data input pin

Data is input from the MSB bit serially.

When FSEL is low, channel 2 data is input.

When FSEL is high, functions as the interface switching pin.

Bit clock input pin

This is the clock for reading in digital audio data bit serially. Also functions as the IC’s system clock when SYSCLK is

fixed low or high.

System clock input pin

This is the system clock that drives the IC. However, in certain modes it is used as the interface switching pin.

(See the timing charts.)

Digital system power supply voltage pin

Output pin for IC testing

When low, digital audio data is input simultaneously from the DATAL and DATAR pins.

When high, digital audio data is input from the DATAL pin in time division mode.

Interface switching pins. (See the timing charts.)

Digital system ground pin

Reference voltage low level pin.

Normally connected to AGND through a capacitor.

Analog system ground pin

Reference voltage low level input pin

No connection

Channel 2 output pin (right channel)

No. 4250-4/11

Timing Charts

LC78816MB, 78816MC

No. 4250-7/11

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