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Ordering number : EN*5212

Preliminary

CMOS LSI

LC78833M, 78833V

Digital Audio 16-Bit D/A Converter

with Built-In Digital Filters

Overview

The LC78833M and LC78833V are CMOS 16-bit D/A

converters with built-in 4× oversampling digital filters.

Functions and Features

[Digital Filter Block]

• 4× oversampling filters: Two FIR filter stages (33rd and

ninth order)

• De-emphasis filter: Supports a 44.1 kHz sampling

frequency (fs).

[D/A Converter Block]

• Dynamic level shifting conversion 16-bit D/A converter

• D/A converters for two channels (synchronized outputs)

on a single chip

• On-chip output operational amplifiers

• System clock: 384fs

• 5-V single-voltage power supply

• Supports low-voltage operation (3.0 V)

• Implemented in a Si gate CMOS process for low power.

Package Dimensions

unit: mm

3036B-MFP20

[LC78833M]

unit: mm

3175A-SSOP24

[LC78833V]

SANYO: MFP20

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V

Parameter

Maximum supply voltage

Maximum input voltage

Maximum output voltage

Operating temperature

Storage temperature

Symbol

VDD max

VIN max

VOUT max

Topr

Tstg

Conditions

SANYO: SSOP24

Ratings

–0.3 to +7.0

–0.3 to VDD + 0.3

–0.3 to VDD + 0.3

–30 to +75

–40 to +125

Unit

V

V

V

°C

°C

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

D3095HA (OT) No. 5212-1/11

Audio Input Waveforms

LC78833M, 78833V

Pin Assignments

No. 5212-4/11

LC78833M, 78833V

3. Initialization

These ICs must be initialized when power is first applied and when the system clock frequency is changed.

Initialization is performed by applying a low level to the INITB pin. That low level must be held for at least one full

cycle of the LRCK signal after the power supply voltage has stabilized and the SYSCLK, BCLK, and LRCK signals

have been applied.

When INITB is low, all 16 bits of the digital filter outputs go to 0, and the D/A converter outputs (CH1OUT and

CH2OUT) go to the analog 0 level, which is a potential equal to (REFH +REFL)/2.

4. System Clock

These ICs support a 384fs system clock. Apply a 384fs clock to the SYSCLK pin.

• CKOUT pin

The SYSCLK and CKOUT pins are related as shown in the figure below.

No. 5212-7/11

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