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Ordering number : EN4624B

CMOS IC

LC78835K, 78835KM

18 Bits Digital Filter and D/A Converter

for Digital Audio

Overview

The LC78835K and 78835KM are 18-bit digital-to-analog

D/A converter CMOS ICs with an on-chip eight-times

oversampling digital filter. The LC78835 and the

LC78835M are pin compatible.

Features

• Digital filter

— 8 fs oversampling filter: 3-stage finite-impulse-

response (FIR) filter design (43rd-, 11th-, and third-

orders)

— De-emphasis filter: Supports fs = 32 kHz, 44.1 kHz,

or 48 kHz

— Soft mute

— Noise shaper

— Supports double-rate sampling

• D/A converter

— Dynamic level-shifting 18-bit digital-to-analog

converter

— On-chip 2-channel D/A converter (with

corresponding output)

— On-chip output op-amp

— Supports 384 fs, 392 fs, 448 fs, or 512 fs system

clock

— Single 5 V supply

— Permits low-voltage operation (3.5 V)

— Low-power silicon-gate CMOS process

Package Dimensions

unit: mm

3092-DIP24W

[LC78835K]

unit: mm

3155-MFP24

[LC78835KM]

SANYO: DIP24W

SANYO: MFP24

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

73696HA (OT)/N1094TH (OT)/82793JN No. 4624-1/14

LC78835K, 78835KM

Electrical Characteristics (2)

at Ta = 25°C, AVDD = DVDD = VrefH 3.5 V, AGND = DGND = VrefH = 0 V, unless otherwise specified

Parameter

Symbol

Conditions

D/A converter resolution

Total harmonic distortion

Dynamic range

Crosstalk

Signal-to-noise ratio

Full-scale output voltage

Power dissipation

Output load resistance

RES

THD

DR

CT

S/N

VFS

Pd

RL

At 1 kHz, 0dB*1

At 1 kHz, –60 dB

At 1 kHz, 0 dB

JIS-A

*2

21, 23 pin

Note: 1. “0 dB” signifies full scale.

2. XIN pulse width (pin 11) 1.0 to 2.5 V, fx = 16.9344 MHz

Test circuit: Based on application circuit

Ratings

Unit

min typ max

18 Bits

0.09 %

90 dB

–85 dB

96 dB

2.1 VP-P

50 75 mW

15 kΩ

Block Diagram

Pin Assignment

No. 4624-4/14

LC78835K, 78835KM

For further details concerning filter characteristics when de-emphasis is on, refer to page 13.

— De-emphasis on/off

De-emphasis on: EMP pin = “H”

De-emphasis off: EMP pin = “L”

— Selection of filter coefficient

FS1 L H H L

FS2 L L H H

fs

44.1 kHz

32 kHz 48 kHz

• Soft Mute

Soft muting is performed using the built-in digital attenuator. The attenuation amount of the attenuator circuit is as

follows:

20 log (ATT/256) dB

Although ATT = 0 to 256, when ATT = 0, attenuation sets to – ∞. If the MUTE pin is set to “H” level, ATT

approaches 0 in single-decreasing increments and the attenuation changes towards – ∞. On the other hand, when

the MUTE pin is set to the “L” level, ATT approaches 256 in single-increasing increments and the attenuation

amount changes to approach 0. The approximate speed during soft mute is 1024/fs.

• Noise Shaper

In order to reduce noise during DF arithmetic output requantization, the first-order noise shaper is utilized.

• Double-Rate Support

When the D/N pin is set to “H” level, CD high-speed playback is supported. At this time, BCLK, LRCK and

DATA are input at double the frequency of normal operating times. The system clock operates at 384 fs and with

a clock speed of 512 fs, double-rate is supported. Note that test mode is enabled for clock speeds of 392 fs and

448fs and double-rate is not supported.

Normal-rate mode: D/N pin = “L”

Double-rate mode: D/N pin = “H”

No. 4624-7/14

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