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PDF CS8422 Data sheet ( Hoja de datos )
| Número de pieza | CS8422 | |
| Descripción | 24-bit 192-kHz Asynchronous Sample Rate Converter | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS8422 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS8422
24-bit, 192-kHz, Asynchronous Sample Rate Converter with
Integrated Digital Audio Interface Receiver
Sample Rate Converter Features
140 dB Dynamic Range
-120 dB THD+N
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios from 6:1 to
1:6
Master Mode Master Clock/Sample Rate Ratio
Support: 64, 96, 128, 192, 256, 384, 512, 768,
1024
16, 18, 20, or 24-bit Data I/O
Dither Automatically Applied and Scaled to
Output Resolution
Multiple Device Outputs are Phase Matched
Digital Audio Interface Receiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF Compatible Receiver
28 kHz to 216 kHz Sample Rate Range
2:1 Differential AES3 or 4:1 S/PDIF Input Mux
De-emphasis Filtering for 32 kHz, 44.1 kHz,
and 48 kHz
Recovered Master Clock Output: 64 x Fs,
96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs,
384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs
49.152 MHz Maximum Recovered Master
Clock Frequency
Ultralow-jitter Clock Recovery
High Input Jitter Tolerance
No External PLL Filter Components Required
Selectable and Automatic Clock Switching
AES3 Direct Output and AES3 TX Pass-
through
On-chip Channel Status Data Buffering
Automatic Detection of Compressed Audio
Streams
Decodes CD Q Sub-Code
VL
SDIN
ISCLK
ILRCK
RX0/RXP0
RX1/RXN0
RX2/RXP1
RX3/RXN1
VA
AGND
DGND
V_REG
Serial
Audio
Input
4:1
MUX
Clock
Generator
Level Translators
Receiver
Clock &
Data
Recovery
(PLL)
2:1
MUX
Sample
Rate
Converter
C or U Data Buffer
(First 5 Bytes)
Format
Detect
Control Port & Registers
Level Translators
3:1
MUX
Serial
Audio
Output
3:1
MUX
Serial
Audio
Output
General
Purpose
Outputs
SDOUT1
OSCLK1
OLRCK1
TDM_IN
SDOUT2
OSCLK2
OLRCK2
GPO0
GPO1
GPO2
GPO3
http://www.cirrus.com
XTI XTO
RMCK
SDA/ SCL/ AD1/ AD0/
CDOUT CCLK CDIN CS
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
NOV '12
DS692F2
1 page  
CS8422
12.4.3 Serial Copy Management System (SCMS) ......................................................................... 69
12.5 Jitter Attenuation .......................................................................................................................... 69
12.6 Jitter Tolerance ............................................................................................................................ 70
12.7 Group Delay ................................................................................................................................. 70
13. PERFORMANCE PLOTS ................................................................................................................... 71
14. PACKAGE DIMENSIONS .................................................................................................................. 80
15. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 80
16. ORDERING INFORMATION .............................................................................................................. 81
17. REFERENCES .................................................................................................................................... 81
18. REVISION HISTORY .......................................................................................................................... 82
LIST OF FIGURES
Figure 1.Non-TDM Slave Mode Timing ..................................................................................................... 19
Figure 2.TDM Slave Mode Timing ............................................................................................................ 19
Figure 3.Non-TDM Master Mode Timing ................................................................................................... 19
Figure 4.TDM Master Mode Timing .......................................................................................................... 19
Figure 5.SPI Mode Timing ........................................................................................................................ 20
Figure 6.I²C Mode Timing ......................................................................................................................... 21
Figure 7.Typical Connection Diagram, Software Mode ............................................................................. 22
Figure 8.Typical Connection Diagram, Hardware Mode ........................................................................... 23
Figure 9.Serial Audio Interface Format – I²S ............................................................................................. 26
Figure 10.Serial Audio Interface Format – Left-Justified ........................................................................... 26
Figure 11.Serial Audio Interface Format – Right-Justified (Master Mode only) ........................................ 26
Figure 12.Serial Audio Interface Format – AES3 Direct Output ................................................................ 26
Figure 13.TDM Master Mode Timing Diagram .......................................................................................... 28
Figure 14.TDM Slave Mode Timing Diagram ............................................................................................ 28
Figure 15.TDM Mode Configuration (All CS8422 outputs are slave) ........................................................ 28
Figure 16.TDM Mode Configuration (First CS8422 output is master, all others are slave) ....................... 28
Figure 17.Single-Ended Receiver Input Structure, Receiver Mode 1 ....................................................... 30
Figure 18.Differential Receiver Input Structure ......................................................................................... 31
Figure 19.C/U Data Outputs ...................................................................................................................... 36
Figure 20.Typical Connection Diagram for Crystal Circuit ........................................................................ 38
Figure 21.Hardware Mode Clock Routing ................................................................................................. 40
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 43
Figure 23.Control Port Timing, I²C Slave Mode Write ............................................................................... 44
Figure 24.Control Port Timing, I²C Slave Mode Read ............................................................................... 44
Figure 25.De-Emphasis Filter Response .................................................................................................. 50
Figure 26.Professional Input Circuit – Differential Mode ........................................................................... 66
Figure 27.Transformerless Professional Input Circuit – Differential Mode ................................................ 66
Figure 28.S/PDIF MUX Input Circuit – Single-Ended ................................................................................ 66
Figure 29.Receiver Mode 1 Single-Ended Input Circuit – Differential Mode ............................................. 66
Figure 30.S/PDIF MUX Input Circuit – Digital Mode ................................................................................. 66
Figure 31.TTL/CMOS Input Circuit – Differential Mode ............................................................................ 66
Figure 32.Receiver Input Attenuation – Single-ended Input ..................................................................... 67
Figure 33.Receiver Input Attenuation – Differential Input ......................................................................... 67
Figure 34.Channel Status Data Buffer Structure ....................................................................................... 68
Figure 35.Flowchart for Reading the E Buffer ........................................................................................... 68
Figure 36.CS8422 PLL Jitter Attenuation Characteristics ......................................................................... 69
Figure 37.Jitter Tolerance Template ......................................................................................................... 70
Figure 38.Wideband FFT –
0 dBFS 1 kHz Tone, 48 kHz:48 kHz ......................................................................................................... 71
Figure 39.Wideband FFT –
0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz .................................................................................................... 71
DS692F2
5
5 Page 
1.2 Hardware Mode
CS8422
RXP0 1
RXN0 2
VA 3
AGND 4
RXP1 5
RXN1 6
SAOF 7
MS_SEL 8
32 31 30 29 28 27 26 25
Thermal Pad
Top-Down View
32-Pin QFN Package
24 OSCLK2
23 SDOUT2
22 VL
21 DGND
20 VD_FILT
19 V_REG
18 TX/U
17 C
9 10 11 12 13 14 15 16
Pin Name
RXP/RXN[1:0]
VA
AGND
SAOF
MS_SEL
NV/RERR
V/AUDIO
XTI
XTO
Pin #
Pin Description
1
2
5
6
AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital
data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0]
comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.
Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that
3 this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of
the recovered clock.
4
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be
connected to a common ground area under the chip.
7
Serial Audio Output Format Select (Input) - Used to select the serial audio output format after RST
is released. See Table 4 on page 42 for format settings.
8
Master/Slave Select (Input) - Used to select Master or Slave settings for the output serial audio ports
after RST is released. See Table 5 on page 42 for format settings.
9
Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by
default, RERR is selected by a 20 k resistor to VL.
Validity Data/AUDIO (Output) - If a 20 k pull-down is present on this pin, it will output serial Validity
10 data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a
20 k pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.
11
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock”
on page 38.
12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38.
DS692F2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS8422.PDF ] | |
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