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부품번호 | ICX252AQF 기능 |
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기능 | Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor | ||
제조업체 | Sony Corporation | ||
로고 | |||
ICX252AQFwww.DataSheet4U.com
Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX252AQF is a diagonal 8.933mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 3.24M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/4.28 second.
Also, number of vertical pixels decimation allows
output of 30 frames per second in high frame rate
readout mode.
R, G, B primary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption of
Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, etc.
20 pin SOP (Plastic)
Pin 1
Features
• Supports frame readout
• High horizontal and vertical resolution
V
• Supports high frame rate readout mode: 30 frames/s,
AF1 mode: 60 frames/s, 50 frames/s,
AF2 mode: 120 frames/s, 100 frames/s
• Square pixel
4
• Horizontal drive frequency: 18MHz
• No voltage adjustments (reset gate and substrate bias are not adjusted.)
Pin 11
H
48
• R, G, B primary color mosaic filters on chip
• High sensitivity, low dark current
Optical black position
• Continuous variable-speed shutter
• Excellent anti-blooming characteristics
(Top View)
• Exit pupil distance recommended range –20 to –100mm
• 20-pin high-precision plastic package
2
8
Device Structure
• Interline CCD image sensor
• Total number of pixels:
2140 (H) × 1560 (V) approx. 3.34M pixels
• Number of effective pixels:
2088 (H) × 1550 (V) approx. 3.24M pixels
• Number of active pixels:
2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm
• Number of recommended record pixels: 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm
aspect ratio 4:3
• Chip size:
8.10mm (H) × 6.64mm (V)
• Unit cell size:
3.45µm (H) × 3.45µm (V)
• Optical black:
Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 28
Vertical 1 (even fields only)
• Substrate material:
Silicon
∗Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00110-PS
ICX252AQF
www.DataSheet4U.com
Bias Conditions
Item Symbol Min. Typ. Max. Unit Remarks
Supply voltage
VDD 14.55 15.0 15.45 V
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power
supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol Min. Typ. Max. Unit Remarks
IDD 2.0 4.5 7.0 mA
Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks
Readout clock voltage VVT
14.55 15.0 15.45 V
1
VVH1, VVH2
–0.05 0 0.05 V
2 VVH = (VVH1 + VVH2)/2
VVH3, VVH4
–0.2 0 0.05 V
2
VVL1, VVL2,
VVL3, VVL4
–8.0 –7.5 –7.0 V
2 VVL = (VVL3 + VVL4)/2
Vertical transfer clock
voltage
VφV
VVH3 – VVH
VVH4 – VVH
6.8 7.5 8.05 V
–0.25
0.1 V
–0.25
0.1 V
2 VφV = VVHn – VVLn (n = 1 to 4)
2
2
VVHH
0.6 V
2 High-level coupling
VVHL
0.9 V
2 High-level coupling
VVLH
0.9 V
2 Low-level coupling
VVLL
0.5 V
2 Low-level coupling
Horizontal transfer
clock voltage
VφH
VHL
VCR
4.75 5.0 5.25 V
–0.05 0 0.05 V
0.8 2.5
V
3
3
3 Cross-point voltage
Reset gate clock
voltage
VφRG
VRGLH – VRGLL
VRGL – VRGLm
3.0
3.3 5.25
0.4
0.5
V
V
V
4
4 Low-level coupling
4 Low-level coupling
Substrate clock voltage VφSUB
21.5 22.5 23.5 V
5
–4–
4페이지 (3) Horizontal transfer clock waveform
tr
Hφ2
twh
90%
tf
10%
Hφ1
VφH
VφH
2
two
ICX252AQF
www.DataSheet4U.com
VCR
twl
VHL
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr twh
tf
RG waveform
VRGH
VRGLH
VRGLL
VRGLm
VφRG
Point A
twl
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
10%
VSUB
0%
(A bias generated within the CCD)
VφSUB
tr twh
–7–
φM
φM
2
tf
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
ICX252AQ | Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor | Sony Corporation |
ICX252AQF | Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor | Sony Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |