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PDF R4F2116 Data sheet ( Hoja de datos )
| Número de pieza | R4F2116 | |
| Descripción | Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0255-0100
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16
H8S/2116Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2116
R4F2116
Rev.1.00
Revision Date: Mar. 02, 2006
1 page  
Configuration of This Manual
www.DataSheet4U.com
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
Product code, Package dimensions, etc.
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 1.00 Mar. 02, 2006 Page v of xl
5 Page 
5.3.3 Break Address Registers A to C (BARA to BARC)........................................... 81
5.3.4
5.3.5
IRQ Sense Control Registers (ISCR16H, ISCR16Lw, wISwC.DRaHta, SISheCeRt4LU)..c..o..m.......... 82
IRQ Enable Registers (IER16, IER) ................................................................... 84
5.3.6 IRQ Status Registers (ISR16, ISR) ..................................................................... 85
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR)
Wake-Up Event Interrupt Mask Registers (WUEMR) ....................................... 87
5.3.8 IRQ Sense Port Select Register 16 (ISSR16)
IRQ Sense Port Select Register (ISSR)............................................................... 91
5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input Interrupt
Status Register (WUESR) Wake-Up Enable Register (WER)............................ 92
5.4 Interrupt Sources................................................................................................................. 93
5.4.1 External Interrupt Sources .................................................................................. 93
5.4.2 Internal Interrupt Sources ................................................................................... 96
5.5 Interrupt Exception Handling Vector Tables ...................................................................... 96
5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 104
5.6.1 Interrupt Control Mode 0 .................................................................................. 106
5.6.2 Interrupt Control Mode 1 .................................................................................. 108
5.6.3 Interrupt Exception Handling Sequence ........................................................... 111
5.6.4 Interrupt Response Times ................................................................................. 112
5.7 Address Breaks ................................................................................................................. 113
5.7.1 Features............................................................................................................. 113
5.7.2 Block Diagram.................................................................................................. 113
5.7.3 Operation .......................................................................................................... 114
5.7.4 Usage Notes ...................................................................................................... 114
5.8 Usage Notes ...................................................................................................................... 116
5.8.1 Conflict between Interrupt Generation and Disabling ...................................... 116
5.8.2 Instructions for Disabling Interrupts ................................................................. 117
5.8.3 Interrupts during Execution of EEPMOV Instruction....................................... 117
5.8.4 Vector Address Switching ................................................................................ 117
5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode................ 118
5.8.6 Noise Canceller Switching................................................................................ 118
5.8.7 IRQ Status Register (ISR)................................................................................. 118
Section 6 Bus Controller (BSC).........................................................................119
6.1 Register Descriptions........................................................................................................ 119
6.1.1 Bus Control Register (BCR) ............................................................................. 119
6.1.2 Wait State Control Register (WSCR) ............................................................... 120
Section 7 I/O Ports .............................................................................................121
7.1 Port 1................................................................................................................................. 126
Rev. 1.00 Mar. 02, 2006 Page xi of xl
11 Page | ||
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