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Ordering number: ENN*6585

CMOS IC

LC7958NC

64-Bit LED Driver for 300 dpi Printers

Preliminary

Overview

LC7958NC is a 64-bit constant current LED driver IC

designed to directly drive LED head array.

The output terminals for LED drive are arranged in

2-row staggered position of 80-µm pitch at one side. It

enables drive of LED Array of 300-dpi in one side

disposition, 600dpi in both sides disposition

Features and Functions

• Logic voltage (VDD): +5 V ± 10 %

• LED drive current (IOH): 5.0 mA (TYP)

• Clock frequency (fc): 10 MHz

• Output current control circuit built in

• Mode switching function by the SEL pin

• Chip size: 1.43 mm × 5.39 mm

• Number of pads: 86

• 64-bit shift register circuit

• 64-bit latch circuit

• Output driver on/off switching function

• Constant current circuit

• 64-bit p-channel open drain LED driver

Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft's

control systems, or other applications whose failure can be reasonably expected to result in serious

physical and/or material damage. Consult with your SANYO representative nearest you before using

any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products specifications of any and all SANYO products described or contained

herein.

42800RM6585-1/11

LC7958NC

Switching Characteristics at VSS = 0 V, VDD1 = VDD2 = 5 V ± 10%, Ta = 0 to 100°C

Parameter

Symbol

Conditions

Ratings

Unit

min typ max

SO output rise time

SO output fall time

tor

SO: CL=10.8pF

tof

50 ns

Output transmission delay

time from STROBE to DO

tpsr STROBE, DO1 to DO64: CL = 10.8

tpsf pF, RF = 10 kΩ

250 ns

Output transmission delay

time from CLOCK2 to SO

tpcr

CLOCK2, SO

tpcf

10 70 ns

CLOCK1→CLOCK2

transmission delay time

tPH CLOC1, CLOCK2, LOAD1, LOAD2:

tPL CL=10.8 pF

40 ns

Equivalent Circuit Block Diagram

VREF

ADJ(+)

Constant

current

circuit

DO1

DO6 4

64-bit constant current driver

VDD2

VDD1

VSS

ADJ(-)

STROBE

SEL

LOAD1

SI

CLOCK1

64-bit latch

64-bit shift register

LOAD2

SO

CLOCK2

6585-4/11

LC7958NC

Ranking by Output Current

1. Test condition: VDD1 = VDD2 = 5.0 V, VREF = 1.8 V, VO = 1.6 V, Ta = 25 °C

2. Ranking determination: The rank is determined by the average ON current (Iave) of the terminals DO1 to DO64 when

the all DO outputs are on.

3. Current width: (Imax - Imin)/(Imax + Imin) ≈ 2.0 %

Rank

ABC

Specification [mA]

-1 -

-3.700 to -3.853

-2 -

-3.854 to -4.011

-3 -

-4.012 to -4.177

14

-

-4.178 to -4.347

25

-

-4.348 to -4.524

36

-

-4.525 to -4.708

471

-4.709 to -4.900

582

-4.901 to -5.100

693

-5.101 to -5.308

7 -4

-5.309 to -5.524

8 -5

-5.525 to -5.749

9 -6

-5.750 to -5.983

- -7

-5.984 to -6.227

- -8

-6.228 to -6.481

- -9

-6.482 to -6.700

***

Rejected article (for the manufacturing process control)

Note: The chips of Ranking No. "*" are marked with the ink

ON Current Deviation in a Chip

Test condition: VDD1 = VDD2 = 5.0 V, VO = 1.6 V, VREF = 1.8 V, Ta = 25 °C

1. Let the average ON current of the terminals DO4, 12, 20, 28, 36, 44, 52, and 60 be Cave, the that of the terminals

DO1, 12, 20, and 28 be Lave, and that of the terminals DO36, 44, 52, and 60 be Rave: then the relationship among

the Cave, Lave, and Rave should be as follows.

| Lave - Cave | / Cave ≤ 2.5 %, | Rave - Cave | / Cave ≤ 2.5 %

2. Let the average ON current of DO1 to DO8, DO29 to DO36, and DO57 to DO64 be I1, I2, and I3, respectively: the

relationship among the I1, I2, and I3 should be as follows.

| In - Iave | / Iave ≤ 2.5 %, Iave: Average ON current of the DO1 to DO64.

In: I2, and I3

6585-7/11

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