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PDF SIS5503 Data sheet ( Hoja de datos )
| Número de pieza | SIS5503 | |
| Descripción | (SIS5501 - SIS5503) PCI System I/O | |
| Fabricantes | Silicon Integrated System | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SIS5503 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Pentium/P54C PCwIw/IwS.DAataCShheeipt4sU.ecotm
1 5501/5502/5503 Overview
SiS5501
SiS5502
SiS5503
PCI/ISA Cache Memory Controller (PCMC)
PCI Local Data Buffer (PLDB)
PCI System I/O (PSIO)
A whole set of the SiS5501, 5502, and 5503 provides fully integrated support for the
Pentium/P54C PCI/ISA system. The chipset is developed by using a very high level of
function integration and system partitioning. With the SiS5501, SiS5502, and SiS5503
chipset, only 12 TTLs (include 3 DRAM address buffer) are required to implement a low cost,
high performance, Pentium/P54C PCI/ISA system. Figure 1 shows the system block diagram.
Address
Data
SRAM
373
CPU
Pentium , P54C
HOST BUS
PCMC
5501
Address/Data
244
DRAM
PLDB
5502
PCI BUS
PSIO
5503
IDE Buffers
XD BUS
245
Address
Data
IDE Drives
PCI Local
Device #1
ISA
Device #1
Figure 1.1 System Block Diagram
PCI Local
Device #2
***
ISA
Device #2
***
ISA BUS
Preliminary V2.0 April 2, 1995
1 Silicon Integrated Systems Corporation
1 page  
SiS5501 PCI/ISA Cache Memwowwry.DaCtaoShnetert4oUl.lceorm
Table 1
Cache Size
64K
128K
256K
512K
512K
1M
1M
2M
Data RAM
8Kx8x8
8Kx8x16
32Kx8x8
32Kx8x16
64Kx8x8
128Kx8x8
64Kx8x16
128Kx8x16
Tag RAM
2Kx8
4Kx8
8Kx8
16Kx8
16Kx8
32Kx8
32Kx8
64Kx8
Alter RAM
2Kx1
4Kx1
8Kx1
16Kx1
16Kx1
32Kx1
32Kx1
64Kx1
Cacheable Size
16M
32M
64M
128M
128M
256M
256M
512M
Interleaved
No
Yes
No
Yes
No
No
Yes
Yes
The PCMC also provides an alternative to save the dirty SRAM chip. This is accomplished by
sharing the alter bit with tag address bits in the same 8-bit wide TAG RAM. System uses this
implementation supports 7 tag address bits and 1 dirty bit. By doing so, the cacheable local
memory sizes are reduced to half of the original sizes as indicated in Table 1.
In reality, the L2 Cacheable DRAM Size is determined by:
1) Max. L2 Cacheable Size as described in table 1.
2) Non-cacheable Area defined in register 57h, 58h, 59h and 5Ah and
3) C, D, E, F Segment Cachability defined in register 53h, 54h, 55h, and 56h.
But, the L1 Cacheable size is only determined by 2), 3), and the maximum DRAM size, i.e.,
512M bytes. Thus, the cycles with address ranging over the L2 Cacheable Size but within the
512M bytes can also be cacheable to L1. The behavior of KEN# is ruled by the L1
Cacheability. Note that only code of C, D, E, F segment is cacheable to L1/L2, and the data
portion of C, D, E, F segment is not cacheable to L1/L2.
Table 2 Burst SRAM Speed Setting
Cycle type
66,60 MHz
Burst read
3/4-1-1-1
3/4-2-2-2
Burst write
3/4-1-1-1
3/4-2-2-2
Single read
3/4
Single write
3/4
50MHz
3/4-1-1-1
3/4-2-2-2
3/4-1-1-1
3/4-2-2-2
3/4
3/4
Note :
1: The burst SRAM speed for 66/60 MHz is 9 ns. For 50MHz, it is 12 ns.
2: X-Y-Y-Y is the recommended setting.
Preliminary V2.0 April 2, 1995
5 Silicon Integrated Systems Corporation
5 Page 
SiS5501 PCI/ISA Cache Memwowwry.DaCtaoShnetert4oUl.lceorm
2. PSIO, REQ3, REQ2, REQ1, REQ0 are requesting bus
GNT0# is asserted
SW1, SW2 and SW3 are toggled to G4, G23 and G1 respectively (since they have been
utilized)
Priority change to G4, G2, G3, G1, G0
3. REQ3, REQ2, REQ1, REQ0 are active
GNT2# is asserted
SW2, SW4 are toggled to G01 and G3 respectively (since they have been utilized)
Priority change to G4, G1, G0, G3, G2
4. REQ3, REQ2, REQ1, REQ0 are active
GNT1# is asserted
SW2, SW3 are toggled to G23 and G0 respectively (since they have been utilized)
Priority change to G4, G3, G2, G0, G1
5. REQ3, REQ2, REQ1, REQ0 are active
GNT3# is asserted
SW2, SW4 are toggled to G01 and G2 respectively (since they have been utilized)
Priority change to G4, G0, G1, G2, G3
6. During 3-5 if there is a request comes from PSIO, the Arbiter will grant bus to PSIO.
CPUCLK
PCICLK
REQ[3:0]#
SIOREQ#
GNT[3:0]#
SIOGNT#
HOLD
CPUHOLD
CPUHLDA
HLDA
FRAME#
IRDY#
PCI Arbiter - Rotation Arbitration scheme
F
F
E
Note : HOLD is internal signal
0
BD
7E
501arbi
A PCI master can burst so long as the target can source/sink the data, and no other agent
requests the bus. However, PCI specifies two mechanisms that cap a master's tenure in the
presence of other requests, so that predictable bus acquisition latency can be achieved. One is
the Master Latency Timer(LT) that is not implemented into the PCMC, the other is the Target
Preliminary V2.0 April 2, 1995
11 Silicon Integrated Systems Corporation
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SIS5503.PDF ] | |
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