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HYS72T512022EP-3.7-B 데이터시트 PDF




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부품번호 HYS72T512022EP-3.7-B 기능
기능 240-Pin Dual Die Registered DDR2 SDRAM Modules
제조업체 Qimonda
로고 Qimonda 로고


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HYS72T512022EP-3.7-B 데이터시트, 핀배열, 회로
March 2007
www.DataSheet4U.com
HYS72T512022EP–3.7–B
HYS72T512022EP–3S–B
240-Pin Dual Die Registered DDR2 SDRAM Modules
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.0




HYS72T512022EP-3.7-B pdf, 반도체, 판매, 대치품
Internet Data Sheet
www.DataSheet4U.com
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
1.2 Description
The Qimonda HYS72T512022EP–[3S/3.7]–B module family
are Registered DIMM (with parity) modules with 30 mm height
based on DDR2 technology.
DIMMs are available as ECC modules in 512M × 72 (4 GB)
organization and density, intended for mounting into 240-Pin
connector sockets.
The memory array is designed with 1-Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. All control and address
signals are re-driven on the DIMM using register devices and
a PLL for the clock distribution. This reduces capacitive
loading to the system bus, but adds one cycle to the SDRAM
timing. Decoupling capacitors are mounted on the PCB
board. The DIMMs feature serial presence detect based on a
serial E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
Product Type1)
Compliance Code2)
TABLE 1
Ordering Information for RoHS Compliant Products
Description
SDRAM
Technology
PC2–4200
HYS72T512022EP–3.7–B
4 GB 2R×4 PC2–4200P–444–12–K0 2 Ranks, ECC
2 × 256 Mbit (×4)
PC2–5300
HYS72T512022EP–3S–B
4 GB 2R×4 PC2–5300P–555–12–K0 2 Ranks, ECC
2 × 256 Mbit (×4)
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T512022EP–3.7–B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–F0”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
DIMM
Density
4 GByte
Module
Organization
512M × 72
Memory
Ranks
2
ECC/
Non-ECC
ECC
TABLE 2
Address Format Table
# of SDRAMs # of row/bank/column
bits
Raw
Card
36 14/3/11
K
Product Type1)
DRAM Components1)2)
DRAM Density
TABLE 3
Components on Modules
DRAM Organisation
HYS72T512022ER
HYB18T2G402BF
2 × 1 Gbit
2 × 256M × 4
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
4

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HYS72T512022EP-3.7-B 전자부품, 판매, 대치품
Internet Data Sheet
www.DataSheet4U.com
Ball No.
Data Signals
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
Name
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
Rev. 1.0, 2007-03
03292007-RHOW-C5L6
HYS72T[512/1G]0x2EP–[3S/3.7]–B
Registerd DDR2 SDRAM Module
Pin Buffer Function
Type Type
I/O SSTL Data Bus 63:0
I/O SSTL Data Input/Output pins
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
7

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HYS72T512022EP-3.7-B

240-Pin Dual Die Registered DDR2 SDRAM Modules

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