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부품번호 | HYS72T512341HKP-5-B 기능 |
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기능 | 240-Pin Registered DDR2 SDRAM Modules | ||
제조업체 | Qimonda | ||
로고 | |||
December 2006
www.DataSheet4U.com
HYS72T512341HHP–[3.7/5]–B
HYS72T512341HJP–[3.7/5]–B
HYS72T512341HKP–[3.7/5]–B
240-Pin Registered DDR2 SDRAM Modules
DDR2 SDRAM
RoHs Compliant Products
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
www.DataSheet4U.com
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
1.2 Description
The Qimonda HYS72T512341H[H/J/K]P–[3.7/5]–B module
family are Very Low Profile Registered DIMM (with parity)
modules with 18,3 mm height based on DDR2 technology.
DIMMs are available as ECC modules in 512M ×72 (4 GB)
organization and density, intended for mounting into 240-Ball
connector sockets.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-ball I2C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
Product Type1)
Compliance Code2)
TABLE 2
Ordering Information for RoHS Compliant Products
Description
SDRAM Technology
PC2–4200
HYS72T512341HHP–3.7–B 4 GB 4R×4 PC2–4200P–444–12–ZZ
4 Rank ECC
4 GB (×4)
HYS72T512341HJP–3.7–B
4 GB 4R×4 PC2–4200P–444–12–ZZ
4 Rank ECC
4 GB (×4)
HYS72T512341HKP–3.7–B 4 GB 4R×4 PC2–4200P–444–12–ZZ
4 Rank ECC
4 GB (×4)
PC2–3200
HYS72T512341HHP–5–B
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 Rank ECC
4 GB (×4)
HYS72T512341HJP–5–B
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 Rank ECC
4 GB (×4)
HYS72T512341HKP–5–B
4 GB 4R×4 PC2–3200P–333–12–ZZ
4 Rank ECC
4 GB (×4)
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512341HJP-3.7-B, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12”, where 4200P
means Registered DIMM modules (Parity bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2.
DIMM Density Module Organization
4 GB
512M ×72
Memory Ranks
4
ECC/
Non-ECC
ECC
# of SDRAMs
TABLE 3
Address Format
# of row/bank/column bits
18 ×4
14/2/11
TABLE 4
Components on Modules
Product Type
DRAM Components
DRAM Density
DRAM Organisation
Note
HYS72T512341HHP
HYS72T512341HJP
HYB18T2G401BHF
512 Mbit
512M ×4
1)
HYS72T512341HKP
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
4
4페이지 Internet Data Sheet
www.DataSheet4U.com
Pin No.
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
Name
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
Rev. 1.0, 2006-12
11032006-VX0M-M6IH
Pin Buffer
Type Type
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
I/O SSTL
Function
Data Bus 63:0
Data Input/Output pins
Data Bus 63:0
7
HYS72T512341H[H/J/K]P-[3.7/5]-B
Registered DDR2 SDRAM Modules
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HYS72T512341HKP-5-B | 240-Pin Registered DDR2 SDRAM Modules | Qimonda |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |