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Ordering number : EN54384465

CMOS LSI

LC80101M

VICS LSI

Overview

The LC80101M is a special-purpose descrambler LSI for

use in VICS systems. FM multiplexed service data that

has had VICS center scrambling applied can be

descrambled and received by inserting this LSI in the

serial interface between the LC72700E and the application

CPU. This architecture also supports reception of regular

transmissions that have not been scrambled. Note that

sample evaluation and product manufacture using this LSI

require a contract with the VICS Center organization.

Functions

• VICS scrambled/unscrambled recognition circuit

• Dedicated VICS descrambler circuit

• CPU interface circuit (CCB: serial)

Package Dimensions

unit: mm

3091A-MFP28

[LC80101M]

SANYO: MFP28

Specifications

Absolute Maximum Ratings

Parameter

Maximum supply voltage

Input voltage

Output voltage

Allowable power dissipation

Operating temperature

Storage temperature

Symbol

VDD max

VIN1

VIN2

VOUT1

VOUT2

Pdmax

Topr

Tstg

Conditions

Ratings

VDD

The CL2, CE2, DI2, RST2, BACKUP, INT-R1, and DI1 pins

–0.3 to +7.0

–0.3 to +7.0

Input pins other than VIN1

The DO2 pin

–0.3 to VDD +0.3

–0.3 to +7.0

Output pins other than VOUT1

Ta ≤ 85°C

–0.3 to VDD +0.3

200

–40 to +85

–55 to +125

Unit

V

V

V

V

V

mW

°C

°C

• CCB is a trademark of SANYO ELECTRIC CO., LTD.

• CCB is SANYO’s original bus format and all the bus

addresses are controlled by SANYO.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

53096HA (OT) No. 5438-1/9

Pin Assignment

LC80101M

Notes on the pull-up resistor used between the LC72700E pin 32 (DO) and this LSI’s pin 5 (DI1)

The value of the pull-up resistor Rp1 must be determined based on the printed circuit board’s floating capacitance and the

LC80101M’s clock. The time tCL for the LC80101M clock is 1.1 µs (corresponding to 450 kHz). This clock is used as

the readout clock output to the LC72700E during the period discussed in note 1 for the basic timing of the external

interface as discussed on page 7. If the tCL of the CL2 clock from the microprocessor is longer than the tCL of the

LC80101M clock, a tCL of 1.1 µs must be used in the formulas below. If the tCL of that clock is shorter than that of the

LC80101M clock, then the tCL of CL2 must be substituted in the formulas below.

For example, in the configuration shown in the figure above, assuming the tCL of CL2 is 1.0 µs (i.e. CL2 = 500 kHz),

then: T = tCL – 555 ns (the LC72700E data output time)

Since T ≈ 2.2 (C1 + C2) R

Rp1 ≈

445 ns

2.2 (C1 + C2)

Assuming that C1 = 10 pF and C2 = 10 pF, then Rp1 will be ≤ 10.1 kΩ. These considerations must be used as guidelines

when determining the value of the pull-up resistor Rp1.

No. 5438-4/9

External Interface Basic Timing

LC80101M

Figure 1

Figure 1 shows how the timing changes between the LC72700E INT-R output and this LSI’s INT-R2 output. This LSI

requires the period indicated as “Note 1”, about 160 µs, following the detection of a falling edge on the INT-R signal to

set up the descrambling processing. It outputs a falling edge on INT-R2 after the note 1 time has elapsed. Serial data

reads and writes are disabled during this period.

Figure 2

Figure 2 shows the basic timing for the external interface. When this LSI is not used and the system is operated based on

the INT-R trigger, if only horizontal data is output, there will be a data readout guaranteed period of 18 – 0.068 = 17.932

ms, and if both horizontal and vertical data are read out, there will be two 9 – 0.068 = 8.932 ms data readout guaranteed

periods, one each for horizontal and vertical data output. When this LSI is used and the system is operated based on the

INT-R2 trigger, these data readout guaranteed periods are shortened by exactly the amount the INT-R2 signal is delayed,

namely 160 µs. When only horizontal data is output, the data readout guaranteed period will be 17.932 – 0.160 = 17.772

ms, and both horizontal and vertical data is output, the data readout guaranteed periods will be 8.932 – 0.160 = 8.772 ms

for both horizontal and vertical data output.

No. 5438-7/9

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