IS24C04A Datasheet PDF - Integrated Silicon Solution
| Part Number | IS24C04A | |
| Description | 1K-bit/2K-bit/4K-bit/8K-bit/16K-bit 2-WIRE SERIAL CMOS EEPROM | |
| Manufacturers | Integrated Silicon Solution | |
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IS24C02A IS24C04A
IS24C08A IS24C16A
®
ISSIwww.DataSheet4U.com
1K-bit/2K-bit/4K-bit/8K-bit/16K-bit
2-WIRE SERIAL CMOS EEPROM
JANUARY 2006
FEATURES
• Two-Wire Serial Interface, I2CTM Compatible
–Bi-directional data transfer protocol
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) Compatible
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max @ 2.5V
• Organization:
–IS24C02A, 256x8 (one block of 256 bytes)
–IS24C04A, 512x8 (two blocks of 256 bytes)
–IS24C08A, 1024x8 (four blocks of 256 bytes)
–IS24C16A, 2048x8 (eight blocks of 256 bytes)
• 16 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Commercial, Industrial and Automotive tempera-
ture ranges
• 8-pin PDIP, 8-pin SOIC, 8-pad DFN, 8-pin
TSSOP, and 8-pin MSOP packages
• Lead-free available
DESCRIPTION
The IS24C02A, IS24C04A, IS24C08A, and
IS24C16A are electrically erasable PROM
devices that use the standard 2-wire interface for
communications. The IS24C02A, IS24C04A,
IS24C08A, and IS24C16A contain a memory array
of 2K-bits (256 x 8), 4K-bits (512 x 8), 8K-bits
(1,024 x 8), and 16K-bits (2,048 x 8), respectively.
Each device is organized into 16 byte pages for
page write mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most application
voltages. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution. The
devices are available in 8-pin PDIP, 8-pin SOIC, 8-
pad DFN, 8-pin MSOP, and 8-pin TSSOP pack-
ages.
The IS24C02A/04A/08A/16A maintains compatibil-
ity with the popular 2-wire bus protocol, so it is
easy to use in applications implementing this bus
type. The simple bus consists of the Serial Clock
wire (SCL) and the Serial Data wire (SDA). Using
the bus, a Master device such as a microcontroller
is usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C02A/04A/08A/16A has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
01/09/06
1
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IS24C02A IS24C04A IS24C08A IS24C16A
ISSI ®
www.DataSheet4U.com
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave address are fixed
as 1010 for the IS2402A/04A/08A/16A.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C02A uses the three bits A0, A1, and A2 in a
comparison with the hard-wired input values on the A0, A1,
and A2 pins. Up to eight IS24C02A units may share the 2-
wire bus.
The IS24C04A uses the bit B0 to address either the upper
or the lower 256 byte block in the device. Also, the bits A1
and A2 are used in a comparison with the hard-wired input
values on the A1 and A2 pins. Up to four IS24C04A units
may share the 2-wire bus.
The IS24C08A uses the bits B0 and B1 to address one of
the four 256 byte blocks in the device. Also, the bit A2 is
used in a comparison with the hard-wired input value on the
A2 pin. Up to two IS24C08A units may share the 2-wire
bus.
The IS24C16A uses the bits B0, B1, and B2 to address one
of the eight 256 byte blocks in the device.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02A/04A/08A/16A) will respond with ACK on the
SDA line. The Slave will pull down the SDA on the ninth
clock cycle, signaling that it received the eight bits of data.
The selected EEPROM then prepares for a Read or Write
operation by monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C02A/04A/08A/
16A. After receiving another ACK from the Slave, the
Master device transmits the data byte to be written into the
address memory location. The IS24C02A/04A/08A/16A
acknowledges once more and the Master generates the
Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.
Page Write
The IS24C02A/04A/08A/16A is capable of 16-byte Page-
Write operation. A Page-Write is initiated in the same manner
as a Byte Write, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 15 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the four lower order data word address
bits are internally incremented by one, while the higher order
bits of the data word address remain constant. If a byte
address is incremented from the last byte of a page, it
returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the Stop
condition, the address counter will “roll over,” and the previously
written data will be overwritten. Once all 16 bytes are
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all
received data is written to the IS24C02A/04A/08A/16A in a
single Write cycle. All inputs are disabled until completion of
the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C02A/04A/08A/16A initiates the internal Write cycle.
ACK polling can be initiated immediately. This involves
issuing the Start condition followed by the Slave address for
a Write operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C02A/04A/
08A/16A has completed the Write operation, an ACK will be
returned and the host can then proceed with the next Read
or Write operation.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
01/09/06
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS24C04A electronic component. |
| Information | Total 21 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS24C04A.PDF Datasheet ] | |
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