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LC82220 데이터시트 PDF
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PDF 형식의 LC82220 자료 제공
| 부품번호 | LC82220 기능 |
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| 기능 | Motion JPEG Decoder LSI | ||
| 제조업체 | Sanyo Semicon Device | ||
| 로고 |  |
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Ordering number : EN*5422
CMOS LSI
LC82220
Motion JPEG Decoder LSI
Preliminaly
Overview
The LC82220 is a single-chip JPEG decoder designed for
wide range of digital video playback applications
including amusement systems, video games and PC JPEG
playback cards. The LC82220 is capable of decoding
JPEG bitstreams of SIF resolution with a picture rate of 30
frames/sec. The digital video output can be formatted for
NTSC, PAL, SECAM, or any other optional video
standard. The complete decoding function is realised with
the LC82220, a standard 8-bit or 16-bit microcontroller
and a bank of DRAM. A typical memory configuration is
a single 128 k × 16 or 256 k × 16 DRAM. The LC82220
also supports efficient video display functions such as
scroll and overlay.
Functions
• Support for JPEG format
• Real-time decoding of motion-JPEG with rate of 30
frames/sec
• Lowest solution cost for amusement, game, PC
systems
• Support for YUV 4:1:1 color format
• YUV or RGB digital video outputs compatible with
optional video format
• Programmable picture and display window format
• Support for trick display: scrolling, overlaying
• Standard 8/16-bit microcontroller interface with DMA
support for compressed data input
• Support SOI and EOI markers
• Direct connect to video DAC
• Direct connect to 2 M or 4 M DRAM as bit and frame
buffers
• Two Q-tables included
• High-speed processing by fixed Huffman tables
Package Dimensions
unit: mm
3182-QFP128E
[LC82220]
SANYO: QIP128E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
62096HA (OT) No. 5422-1/6
 
LC82220
Continued from preceding page.
Pin No.
Symbol
I/O
Function
56
DB7
O
57
DB6
O
58
DB5
O
59
DB4
O
Pixel data bus B (V)
60
DB3
O
61
DB2
O
62
DB1
O
63
DB0
O
64 VSS
Ground
65 VDD
+5V power supply
66
ZBLANK
O Blanking signal
67
ZPXEN
I Pixel data enable signal
68
PXCLK
I Pixel clock
69
ZVSYNC
I Vertical synchronizing signal
70
ZHSYNC
I Horizontal synchronizing signal
71
DG7
O
72
DG6
O
73
DG5
O
74
DG4
O
Pixel data bus G (U)
75
DG3
O
76
DG2
O
77
DG1
O
78
DG0
O
79
TEST2
I Test pin
80 VDD
+5 V power supply
81 VSS
Ground
82
DR7
O
83
DR6
O
84
DR5
O
85
DR4
O Pixel data bus R (Y)
86
DR3
O
87
DR2
O
88
DR1
O
89
DR0
O
90 VSS
Ground
91
ZOE
O Memory output enable
92
ZWEL
O Memory write enable (L)
93
ZRAS
O Row address strobe
94
ZCASL
O Column address strobe (L)
95 ZWEH/ZCASH O Memory write enable (H)/column address strobe (H)
96 VDD
+5 V power supply*1
97 VSS
Ground
98
MD15
I/O
99
MD14
I/O
100
MD13
I/O Frame memory interface data bus
101
MD12
I/O
102
MD11
I/O
103
MD10
I/O
104 VDD
+5 V power supply
105 VSS
Ground
106
MD9
I/O
107
MD8
I/O
108
MD7
I/O Frame memory interface data bus
109
MD6
I/O
110
MD5
I/O
111
MD4
I/O
Continued on next page.
No. 5422-4/6
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관련 데이터시트
| 부품번호 | 상세설명 및 기능 | 제조사 |
| LC82220 | Motion JPEG Decoder LSI | Sanyo Semicon Device |
| LC82221 | Motion JPEG Decoder | Sanyo Semicon Device |
| DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |