PDF ADF7011 Data sheet ( Hoja de datos )

Número de pieza	ADF7011
Descripción	High Performance ISM Band ASK/FSK/GFSK Transmitter IC
Fabricantes	Analog Devices
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No Preview Available ! High Performance ISM Bandwww.DataSheet4U.com ASK/FSK/GFSK Transmitter IC ADF7011 FEATURES Single Chip Low Power UHF Transmitter Frequency Band 433 MHz to 435 MHz 868 MHz to 870 MHz On-Chip VCO and Fractional-N PLL 2.3 V to 3.6 V Supply Voltage Programmable Output Power –16 dBm to +12 dBm, 0.3 dB Steps Data Rates up to 76.8 kbps Low Current Consumption 29 mA at +10 dBm at 433.92 MHz Power-Down Mode (<1 ␮A) 24-Lead TSSOP Package Hooks to External VCO for < 1.4 GHz Operation APPLICATIONS Low Cost Wireless Data Transfer Wireless Metering Remote Control/Security Systems Keyless Entry GENERAL DESCRIPTION The ADF7011 is a low power OOK/ASK/FSK/GFSK UHF transmitter designed for use in ISM band systems. It contains and integrated VCO and Σ-∆ fractional-N PLL. The output power, channel spacing, and output frequency are program- mable with four 24-bit registers. The fractional-N PLL enables the user to select any channel frequency within the European 433 MHz and 868 MHz bands, allowing the use of the ADF7011 in frequency hopping systems. The fractional-N also allows the transmitter to operate in the less congested sub-bands of the 868 MHz to 870 MHz SRD band. It is possible to choose from the four different modulation schemes: Binary or Gaussian Frequency Shift Keying (FSK/ GFSK), Amplitude Shift Keying (ASK), or On/Off Keying (OOK). The device also features a crystal compensation register that can provide ± 1 ppm resolution in the output frequency. Indirect temperature compensation of the crystal can be accom- plished inexpensively using this register. Control of the four on-chip registers is via a simple 3-wire inter- face. The devices operate with a power supply ranging from 2.3 V to 3.6 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM CREG OSC1 OSC2 ، CLK CLKOUT CPVDD CPGND CPOUT VCOIN CVCO VCOGND OOK/ASK VDD DVDD DGND TxCLK TxDATA LE DATA CLK REV. 0 ، R PFD/ CHARGE PUMP OOK/ASK FSK/GFSK ، FRACTIONAL-N SIGMA-DELTA SERIAL INTERFACE FREQUENCY COMPENSATION CENTER FREQUENCY CE ADF7011 AGND VCO RFOUT PA RFGND LDO REGULATOR CREG LOCK DETECT MUXOUT MUXOUT RSET TEST Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page PIN CONFIGURATION RSET 1 24 CREG CPVDD 2 23 CVCO CPGND 3 CPOUT 4 TSSOP 22 VCOIN 21 AGND CE 5 ADF7011 20 RFOUT DATA 6 TOP VIEW 19 RFGND CLK 7 (Not to Scale) 18 DVDD LE 8 17 TEST TxDATA 9 TxCLK 10 16 VCOGND 15 OSC1 MUXOUT 11 14 OSC2 DGND 12 13 CLKOUT ADF7011 www.DataSheet4U.com Pin No. Mnemonic 1 RSET 2 CPVDD 3 CPGND 4 CPOUT 5 CE 6 DATA 7 CLK 8 LE 9 TxDATA 10 TxCLK 11 MUXOUT 12 DGND 13 CLKOUT 14 OSC2 PIN FUNCTION DESCRIPTIONS Function External Resistor to Set Change Pump Current and Some Internal Bias Currents. Use 4.7 kΩ as default: ICP MAX = 9.5 RSET So, with RSET = 4.7 kΩ, ICP MAX = 2.02 mA. Charge Pump Supply. This should be biased at the same level as RFOUT and DVDD. The pin should be decoupled with a 0.1 µF capacitor as close to the pin as possible. Charge Pump Ground. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to function. This is the only way to power down the regulator circuit. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Digital data to be transmitted is input on this pin. GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7011. The clock is provided at the same frequency as the data rate. This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled reference frequency to be accessed externally. Used commonly for system debug. See the Function Regis- ter Map. Ground Pin for the RF Digital Circuitry. The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can be reduced with a series RC. For 4.8 MHz output clock, a series 50 Ω into 10 pF will reduce spurs to < –50 dBc. Defaults on power-up to divide by 16. Oscillator Pin. If a single-ended reference (such as a TCXO) is used, it should be applied to this pin. When using an external signal generator, a 51 Ω resistor should be tied from this pin to ground. The XOE bit in the R register should set high when using an external reference. REV. 0 –5– 5 Page RF N Register ADF7011 www.DataSheet4U.com 8-BIT INTEGER-N 12-BIT FRACTIONAL-N CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LDP V1 N8 N7 N6 N5 N4 N3 N2 N1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C2 (0) C1 (1) M12 0 0 0 . . . 1 1 1 1 M11 0 0 0 . . . 1 1 1 1 M10 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... e.g., SETTING F = 0 IN FSK MODE TURNS ON THE ⌺-⌬ WHILE THE PLL IS AN INTEGER VALUE M3 M2 M1 MODULUS DIVIDE RATIO 1 00 1 01 1 10 ... ... ... 1 00 4 5 6 . . . 4092 1 01 4093 1 10 4094 1 11 4095 e.g., MODULUS DIVIDE RATIO = 2048 –> FRACTION 1/2 N8 N7 N6 N5 N4 N3 N2 N1 N COUNTER DIVIDE RATIO 00 0 1 1 1 1 1 00 1 0 0 0 0 0 00 1 0 0 0 0 1 00 1 0 0 0 1 0 .. . . . . . . .. . . . . . . .. . . . . . . 11 1 1 1 1 0 1 31 32 33 34 . . . 253 11 1 1 1 1 1 0 254 11 1 1 1 1 1 1 255 V1 VCO BAND (MHz) 0 866–870 1 433–435 LDP 0 1 LOCK DETECT PRECISION 3 CYCLES < 15ns 5 CYCLES < 15ns THE N VALUE CHOSEN IS A MINIMUM OF P2 + 3P + 3. FOR PRESCALER = 8/9, THIS MEANS A MINIMUM N DIVIDE OF 91. REV. 0 –11– 11 Page

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