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Ordering number : EN5663

CMOS IC

LC83026E

Digital Signal Processor for Karaoke Systems

Overview

The LC83026E provides the audio signal processing

required in karaoke systems, including pitch shift,

microphone echo, voice muting, and simple surround

simulation. It is a special-purpose DSP that implements

karaoke processing with the addition of a single external

256-Kb DRAM. The LC83026E includes on-chip A/D and

D/A converters and supports both digital and analog

inputs and outputs. Its functions and characteristics can be

modified to match the needs of the end product by sending

coefficient data from the microcontroller over a serial

interface.

Features

• Application features

— Pitch shift

The LC83026E supports pitch shifting of ±15

quarter tone steps, or ±1 octave in scale tone units as

specified by command data. This pitch shifting can

be applied either to the music track or to the

microphone input. It is also possible to set up pitch

shifting of ±1 octave in arbitrary steps by setting

coefficient values.

— Microphone echo

The LC83026E can apply echo processing to the

input signal from the microphone A/D converter.

The echo coefficients, including amount of echo and

delay time, can be set.

— Voice muting

The LC83026E provides attenuation of monaural

components in the music signal. This allows CDs

that include vocals to be used for karaoke. The voice

muting function is turned on or off by command data

transferred over the serial interface.

— Simple surround

The LC83026E implements a simple surround

simulation function by adding delay components to

the music signal. The LC83026E includes six sets of

simple surround coefficients as preset data, and these

can be selected and switched using command data

transferred over the serial interface. User-original

surround effects can be implemented by setting

coefficients, but the algorithm is fixed.

— Versatile input mixing

The LC83026E supports hybrid mixing of digital

music inputs and analog music inputs for both the

left and right channels to support the processing of a

wide range of disks.

• Audio inputs and outputs

— Inputs: Digital

One system (stereo)

A/D converters Three channels

— Outputs: Digital One system (stereo)

D/A converters Two channels

— A/D converters

Second-order delta-sigma modulation

Three channels

— D/A converters

2× oversampling digital filters + third-order noise

shaper system

Two channels

• Master clock: 768fs

• External memory: Up to two 256K (64K × 4 bits)

external DRAMs can be used.

• Microcontroller input: Synchronous 8-bit serial data

• Power-supply voltage: 5V single-voltage supply

• Package: QFP80E

Package Dimensions

unit: mm

3174-QFP80E

[LC83026E]

SANYO: QIP80E

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN

63097HA(OT) No. 5663-1/16

LC83026E

Continued from preceding page.

Pin Pin No. I/O

Function

DVDD1 to 3 17, 18, 72 — Digital block VDD (Must be connected to +5 V.)

<Make connections as short as possible so that no potential differences occur between any of the VDD pins.>

DVSS1 to 3 21, 48, 73 — Digital block VSS (Must be connected to ground.)

<Make connections as short as possible so that no potential differences occur between any of the VSS pins.>

ADLVDD

35 — A/D converter VDD (left channel) (Connect to +5 V.)

ADRVDD

41 — A/D converter VDD (right channel) (Connect to +5 V.)

ADMVDD 46 — A/D converter VDD (microphone) (Connect to +5 V.)

DALVDD

24 — D/A converter VDD (left channel) (Connect to +5 V.)

DARVDD

31 — D/A converter VDD (right channel) (Connect to +5 V.)

Design the wiring so that potential differences do

not occur between the analog system VDD pins and

either other analog system VDD pins or the digital

system VDD pins.

ADLVSS

33 — A/D converter VSS (left channel) (Connect to ground.)

ADRVSS

39 — A/D converter VSS (right channel) (Connect to ground.) Design the wiring so that potential differences do

ADMVSS

44

— A/D converter VSS (microphone) (Connect to ground.)

not occur between the analog system VSS pins and

DALVSS

27

— D/A converter VSS (left channel) (Connect to ground.)

either other analog system VSS pins or the digital

system VSS pins.

DARVSS

28 — D/A converter VSS (right channel) (Connect to ground.)

Pin Circuits

Pins Specifications

ASO, LRCKO, BCKO, RAS, CAS,

DREAD, DWRT, FS384O, A0 to A8

TTL output

P3, P4, SIAK

CMOS intermediate current output

Circuit

Output data

ADL2, ADL3, ADM2, ADM3, ADR2,

ADR3

Analog output

DALP, DALN, DARP, DARN

Output data

Output data

SI, SICK, SIRQ, SRDY, (OSC1)

FS384I, BCKI, ASI, LRCKI

Schmitt input

Low Schmitt input

TEST1 to TEST5

Normal input

Input data

Input data

RES

SELC, SAIF, SAOF

Input with built-in pull-up resistor

Input with built-in pull-down resistor

Input data

Input data

Continued on next page.

No. 5663-4/16

Continued from preceding page.

Parameter

[External DRAM Access Timing]

RAS high-level pulse width

RAS low-level pulse width

CAS high-level pulse width

CAS low-level pulse width

CAS cycle time

RAS to CAS delay time

CAS hold time

RAS hold time

RAS address setup time

RAS address hold time

CAS address setup time

CAS address hold time

DWRT pulse width

Write command setup time

Write command hold time

Output data setup time

Output data hold time

Crystal oscillator

Current drain

LC83026E

Symbol

Conditions

tRP

tRAS

tCP

tCAS

tPC

tRCD

tCSH

tRSH

tASR

tRAH

tASC

tCAH

tWP

tWCS

tWCH

tDSO

tDHO

C1

C2

L

IDD

Output timing to the external DRAM.

See Figure 8.

Output timing to the external DRAM.

See Figure 8.

OSC1 and OSC2. See Figure 2.

For VDD1, VDD2, and VDD3 when

operating at 33.8688 MHz.

Ratings

min typ

80

700

50

95

175

60

170

95

60

20

30

90

95

12

65

30

100

13

29

1.5

60

Unit Notes

max

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

ns 7

pF 8

pF 8

µH 8

95 mA 9

Electrical Characteristics 2 at Ta = 25°C, all VDD = 5.0 V, all VSS = 0 V unless otherwise specified

Parameter

[A/D Converter Block]

Total harmonic distortion

Signal-to-noise ratio

Crosstalk

[D/A Converter Block]

Total harmonic distortion

Signal-to-noise ratio

Crosstalk

Symbol

Conditions

A-THD

A-S/N

A-C · T

1 kHz, at 0 dB

1 kHz, at 0 dB

1 kHz, at 0 dB

D-THD

D-S/N

D-C · T

1 kHz, at 0 dB

1 kHz, at 0 dB

1 kHz, at 0 dB

Ratings

min typ

0.05

75 80

–75

0.01

85

–80

Unit Notes

max

% 10

dB 10,11

dB 10,11

% 10

dB 10,11

dB 10,11

Notes:

1. TTL output level pins: ASO, FS384O, BCKO, LRCKO, D0 to D7, A0 to A8, RAS, CAS, DREAD, DWRT

2. CMOS intermediate current output pins: P3, P4, SIAK

3. N-channel open drain intermediate current output pins: P0 to P2

4. Low Schmitt input pins: BCKI, ASI, LRCKI, D0 to D7, FS384I

5. Normal input pins: P0 to P2, TEST1 to TEST5, SELC, SAIF, SAOF

6. Schmitt input pins: RES, SI, SICK, SIRQ, SRDY, OSC1

7. When the load capacitance is 50 pF.

8. The values for the oscillator capacitors C1 and C2 include the line capacitances.

9. The typical values for the current drain are for VDD = 5 V, room temperature, and typical samples.

10. Fs = 44.1 kHz and 20 kHz low-pass filter used. Measurement is with the external circuit structure and constants in the Sanyo evaluation board.

11. With the weight A filter used.

No. 5663-7/16

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