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PDF AT90PWM1 Data sheet ( Hoja de datos )
| Número de pieza | AT90PWM1 | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR ® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 8K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• Peripheral Features
– Two 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution
Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25 Hz Step Width at 150 kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture
Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– Master/Slave SPI Serial Interface
– 10-bit ADC
• 8 Single Ended Channels and 1 Fully Differential ADC Channel Pair
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channel)
• Internal Reference Voltage
– Two Analog Comparator with Resistor-Array to Adjust Comparison Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes)
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator ( 8 MHz)
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90PWM1
4378C–AVR–09/08
1 page  
AT90PWM1
Table 3-1.
QFN32
Pin out description (Continued)
S024 Pin Number Mnemonic
12 12 PD4
13 13 PD5
14 14 PD6
15 15 PD7
31 2 PE0
10 10 PE1
11 11 PE2
Type
I/O
I/O
I/O
I/O
I/O or I
I/O
I/O
Name, Function & Alternate Function
ADC1 (Analog Input Channel 1)
RXD (Dali/UART Rx data)
ICP1A (Timer 1 input capture)
SCK_A (Programming & alternate SPI Clock)
ADC2 (Analog Input Channel 2)
ACMP2 (Analog Comparator 2 Positive Input )
ADC3 (Analog Input Channel 3 )
ACMPM reference for analog comparators
INT0
ACMP0 (Analog Comparator 0 Positive Input )
RESET (Reset Input)
OCD (On Chip Debug I/O)
XTAL1: XTAL Input
OC0B (Timer 0 Output Compare B)
XTAL2: XTAL OuTput
ADC0 (Analog Input Channel 0)
4. Overview
The AT90PWM1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90PWM1 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
4378C–AVR–09/08
5
5 Page 
AT90PWM1
5.4 Status Register
The Status Register contains information about the result of the most recently executed arith-
metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
4378C–AVR–09/08
11
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| PDF Descargar | [ Datasheet AT90PWM1.PDF ] | |
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