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PDF AT90PWM2B Data sheet ( Hoja de datos )
| Número de pieza | AT90PWM2B | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power Atmel® AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 129 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 8K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• Peripheral Features
– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit
Resolution Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25 Hz Step Width at 150 kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture
Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– Programmable Serial USART
• Standard UART mode
• 16/17 bit Biphase Mode for DALI Communications
– Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)
• Internal Reference Voltage
– 10-bit DAC
– Two or three Analog Comparator with Resistor-Array to Adjust Comparison
Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes)
8-bit Atmel
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90PWM2
AT90PWM3
AT90PWM2B
AT90PWM3B
4317K–AVR–03/2013
1 page  
AT90PWM2/3/2B/3B
3.1 Pin Descriptions
Table 3-1. Pin out description
S024 Pin
Number
7
18
6
SO32 Pin
Number
9
24
8
QFN32 Pin
Number
5
20
4
Mnemonic
GND
AGND
VCC
17 23 19 AVCC
19 25 21 AREF
8 12 8 PBO
9 13 9 PB1
16 20 16 PB2
20 27 23 PB3
21 28 24 PB4
22 30 26 PB5
23 31 27 PB6
24 32 28 PB7
Type
Power
Power
power
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name, Function & Alternate Function
Ground: 0V reference
Analog Ground: 0V reference for analog part
Power Supply:
Analog Power Supply: This is the power supply voltage for analog
part
For a normal use this pin must be connected.
Analog Reference : reference for analog converter . This is the
reference voltage of the A/D converter. As output, can be used by
external analog
MISO (SPI Master In Slave Out)
PSCOUT20 output
MOSI (SPI Master Out Slave In)
PSCOUT21 output
ADC5 (Analog Input Channel5 )
INT1
AMP0- (Analog Differential Amplifier 0 Input Channel )
AMP0+ (Analog Differential Amplifier 0 Input Channel )
ADC6 (Analog Input Channel 6)
INT 2
ADC7 (Analog Input Channel 7)
ICP1B (Timer 1 input capture alternate input)
PSCOUT11 output (see note 1)
PSCOUT01 output
ADC4 (Analog Input Channel 4)
SCK (SPI Clock)
4317K–AVR–03/2013
5
5 Page 
AT90PWM2/3/2B/3B
5. AVR CPU Core
5.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2 Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
Data
SRAM
EEPROM
I/O Module1
I/O Module 2
I/O Module n
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
4317K–AVR–03/2013
11
11 Page | ||
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| PDF Descargar | [ Datasheet AT90PWM2B.PDF ] | |
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