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PDF LM5025A Data sheet ( Hoja de datos )
| Número de pieza | LM5025A | |
| Descripción | Active Clamp Voltage Mode PWM Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 2004
www.DataSheet4U.com
LM5025A
Active Clamp Voltage Mode PWM Controller
General Description
The LM5025A is a functional variant of the LM5025 active
clamp PWM controller. The functional differences of the
LM5025A are: The CS1 and CS2 current limit thresholds
have been increased to 0.5V. The internal CS2 filter dis-
charge device has been disabled and no longer operates
each clock cycle. The internal VCC and VREF regulators
continue to operate when the line UVLO pin is below thresh-
old.
The LM5025A PWM controller contains all of the features
necessary to implement power converters utilizing the Active
Clamp / Reset technique. With the active clamp technique,
higher efficiencies and greater power densities can be real-
ized compared to conventional catch winding or RDC clamp
/ reset techniques. Two control outputs are provided, the
main power switch control (OUT_A) and the active clamp
switch control (OUT_B). The two internal compound gate
drivers parallel both MOS and Bipolar devices, providing
superior gate drive characteristics. This controller is de-
signed for high-speed operation including an oscillator fre-
quency range up to 1MHz and total PWM and current sense
propagation delays less than 100ns. The LM5025A includes
a high-voltage start-up regulator that operates over a wide
input range of 13V to 90V. Additional features include: Line
Under Voltage Lockout (UVLO), softstart, oscillator UP/
DOWN sync capability, precision reference and thermal
shutdown.
Features
n Internal Start-up Bias Regulator
n 3A Compound Main Gate Driver
n Programmable Line Under-Voltage Lockout (UVLO) with
Adjustable Hysteresis
n Voltage Mode Control with Feed-Forward
n Adjustable Dual Mode Over-Current Protection
n Programmable Overlap or Deadtime between the Main
and Active Clamp Outputs
n Volt x Second Clamp
n Programmable Soft-start
n Leading Edge Blanking
n Single Resistor Programmable Oscillator
n Oscillator UP / DOWN Sync Capability
n Precision 5V Reference
n Thermal Shutdown
Packages
n TSSOP-16
n LLP-16 (5x5 mm) Thermally Enhanced
Typical Application Circuit
Simplified Active Clamp Forward Power Converter
20107401
© 2004 National Semiconductor Corporation DS201074
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND
VCC to GND
CS1, CS2 to GND
All other inputs to GND
ESD Rating (Note 2)
-0.3V to 105V
-0.3V to 16V
-0.3 to 1.00V
-0.3 to 7V
Human Body Model
Storage Temperature Range
Junction Temperature
2kV
-5w5˚wCwto.D1a5t0a˚SCheet4U.com
150˚C
Operating Ratings (Note 1)
VIN Voltage
External Voltage Applied to VCC
Operating Junction Temperature
13 to 90V
8 to 15V
-40˚C to +125˚C
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (Note 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator
VCC Reg
I-VIN
VCC Regulation
VCC Current Limit
Startup Regulator
Leakage (external Vcc
No Load
(Note 4)
VIN = 100V
7.3 7.6 7.9 V
20 25
mA
165 500 µA
Supply)
VCC Supply
VCC Under-voltage
Lockout Voltage
VCC Reg -
220mV
VCC Reg -
120mV
V
(positive going Vcc)
VCC Under-voltage
Hysteresis
1.0 1.5 2.0 V
VCC Supply Current
(ICC)
Reference Supply
Cgate = 0
4.2 mA
VREF
Ref Voltage
Ref Voltage
Regulation
IREF = 0 mA
IREF = 0 to 10mA
4.85
5
5.15
V
25 50 mV
Ref Current Limit
10 20
mA
Current Limit
CS1 Prop CS1 Delay to Output CS1 Step from 0 to 0.6V
40 ns
Time to onset of OUT
Transition (90%)
CS2 Prop CS2 Delay to Output
Cgate = 0
CS2 Step from 0 to 0.6V
50 ns
Time to onset of OUT
Transition (90%)
Cycle by Cycle
Cgate = 0
0.45
0.5
0.55
V
Threshold Voltage
(CS1)
Cycle Skip Threshold Resets SS capacitor; auto
0.45
0.5
0.55
V
Voltage (CS2)
restart
Leading Edge
50 ns
Blanking Time (CS1)
CS1 Sink Impedance CS1 = 0.4V
30 50 Ω
(clocked)
CS1 Sink Impedance CS1 = 0.6V
15 30 Ω
(Post Fault Discharge)
5 www.national.com
5 Page 
PWM Outputs (Continued)
www.DataSheet4U.com
FIGURE 1.
20107412
Compound Gate Drivers
The LM5025A contains two unique compound gate drivers,
which parallel both MOS and Bipolar devices to provide high
drive current throughout the entire switching event. The Bi-
polar device provides most of the drive current capability and
provides a relatively constant sink current which is ideal for
driving large power MOSFETs. As the switching event nears
conclusion and the Bipolar device saturates, the internal
MOS device continues to provide a low impedance to com-
pete the switching event.
During turn-off at the Miller plateau region, typically around
2V - 3V, is where gate driver current capability is needed
most. The resistive characteristics of all MOS gate drivers
are adequate for turn-on since the supply to output voltage
differential is fairly large at the Miller region. During turn-off
however, the voltage differential is small and the current
source characteristic of the Bipolar gate driver is beneficial to
provide fast drive capability.
the internal 5V reference and COMP, can be used as the
pull-up for an optocoupler. The comparator polarity is such
that 0V on the COMP pin will produce a zero duty cycle on
both gate driver outputs.
Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp
signal (RAMP) to a fixed 2.5V reference. By proper selection
of RFF and CFF, the maximum ON time of the main switch
can be set to the desired duration. The ON time set by Volt
x Second Clamp varies inversely with the line voltage be-
cause the RAMP capacitor is charged by a resistor con-
nected to Vin while the threshold of the clamp is a fixed
voltage (2.5V). An example will illustrate the use of the Volt x
Second Clamp comparator to achieve a 50% duty cycle limit,
at 200KHz, at a 48V line input: A 50% duty cycle at a 200KHz
requires a 2.5µs of ON time. At 48V input the Volt x Second
product is 120V x µs (48V x 2.5µs). To achieve this clamp
level:
RFF x CFF = VIN x TON / 2.5V
48 x 2.5µ / 2.5 = 48µ
Select CFF = 470pF
RFF = 102kΩ
The recommended capacitor value range for CFF is 100pF
to 1000pF.
The CFF ramp capacitor is discharged at the conclusion of
every cycle by an internal discharge switch controlled by
either the internal clock or by the V x S Clamp comparator,
whichever event occurs first.
20107413
PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to
the loop error signal (COMP). This comparator is optimized
for speed in order to achieve minimum controllable duty
cycles. The internal 5kΩ pull-up resistor, connected between
Current Limit
The LM5025A contains two modes of over-current protec-
tion. If the sense voltage at the CS1 input exceeds 0.5V the
present power cycle is terminated (cycle-by-cycle current
limit). If the sense voltage at the CS2 input exceeds 0.5V, the
controller will terminate the present cycle, discharge the
softstart capacitor and reduce the softstart current source to
1µA. The softstart (SS) capacitor is released after being fully
discharged and slowly charges with a 1µA current source.
When the voltage at the SS pin reaches approximately 1V,
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LM5025A.PDF ] | |
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