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PDF SH3003 Data sheet ( Hoja de datos )
| Número de pieza | SH3003 | |
| Descripción | MicroBuddy Support IC for Microcontrollers | |
| Fabricantes | Semtech | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH3003 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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POWER MANAGEMENT
SH3003
MicroBuddy® Support IC
for Mwiwcwr.DoactaoShneett4rUo.collmers
Description
Features
Three components make a complete system: any
microcontroller, the SH3003, and a bypass capacitor. This
low-cost system would consume very little power and have
clock-frequency accuracy of ± 0.5%. A fourth component,
a 32.768kHz crystal, raises the clock frequency accuracy
to ± 0.0256% (± 256 ppm).
The SH3003 can operate completely stand-alone, or un-
der control of the microcontroller. A single-wire interface
handles both bi-directional communications and the in-
terrupt/wake-up signal from the SH3003. The SH3003
stores all configuration, calibration, parameters, and sta-
tus information in a 36-byte bank of control registers. On
reset, most of these are reloaded with defaults from the
factory-set non-volatile memory. The microcontroller can
change any settings on the fly. If some of the settings must
remain fixed, a comprehensive set of write-protect bits is
provided for several related groups of registers (with both
permanent write-inhibit and lock/unlock capabilities).
A backup power source may also be connected to the
SH3003. The IC can directly accommodate 2/3-cell zinc-
carbon/alkaline, 2/3-cell mercury, 2/3/4-cell NiCd/NiMH,
one cell Li/Li+ batteries, or a super cap.
Highly integrated
• IC - 3mm x 3mm x 0.9mm, 16-lead MLP
(QFN) package
CPU Supervisor
• Low VDD reset programmable from 2.3V to 4.3V
• Watchdog timer with programmable time out
periods
• Both active-high and active-low reset outputs
Clock Management System
• Replaces high-frequency (HF) crystal or resonator
• Programmable clock output from 32.768kHz to
16MHz
• Speed shift between multiple clock frequencies
• Adjustable spectrum spreading for EMI reduction
• Directly supports microcontroller STOP function
• Deep sleep with instantaneous auto-wakeup
Real-Time Support
• 179 year real-time clock, battery-backup capable
• Dedicated 32.768kHz buffered clock output
• Built-in trim for 32.768kHz oscillator to ±4ppm
• Programmable periodic interrupt/wakeup timer
The programmable SH3003 MicroBuddy® (μBuddy®)
provides all mandatory microcontroller support
functions:
CPU Supervisor
Clock Management System
Real-Time Support
Auxiliary Functions
Applications
Auxiliary Functions
• 4-byte (32-bit) scratchpad RAM, loaded on reset
with factory-set value (zero or optional ID code)
• All settings programmable in real time, defaults
restored from nonvolatile memory on reset
Operates from 2.3V to 5.5V
• IDD < 850μA /2MHz, < 3mA / 16MHz, <10μA/
standby - IBUP < 2μA / IBSB <50nA (battery back
up/standby)
Home automation and security
Consumer products
Portable/handheld computers
Industrial equipment
Any microcontroller-based product
May 23, 2006
1 www.semtech.com
1 page  
SH3003
POWER MANAGEMENT
Electrical Characteristics (continued)
Programmable Reset
Parameter
VDD switching threshold after power-up
VDD switching threshold for min code VBO(MIN)
VDD switching threshold for max code
VDD threshold resolution
VDD hysteresis
Falling VDD threshold switch delay
Threshold DAC settling time
Minimum VDD for valid NRST and RST
www.DataSheet4U.com
Symbol
Min
Typ
Max Units
VBO(PUP) 2.3 V
VBO(MIN) 2.27 2.3 2.33 V
VBO(MAX) 4.2 4.3 4.4 V
VRES
33 mV
VHYS
50 mV
Td 2.5 μs
TDAC
4 ms
VDD(MIN)
1V
High-Frequency Oscillator (HFO)
Parameter
Symbol
Min
Minimum operating freq. (start-up default = 16MHz)
Maximum operating frequency
Frequency resolution
Programmed frequency accuracy at 25°C
Frequency drift over temperature and supply
CLKOUT cycle-to-cycle jitter (spread spectrum off)
FMIN
FMAX
FRES
FST
FDRIFT
J
16.8
-0.3
Start-up time from standby
Settling time to 0.1% after HF digitally-controlled
oscillator (DCO) code change
CLKOUT duty cycle
TSTART
TSETT
DC
40
Frequency temperature stability
Short-term frequency stability
Minimum spread spectrum range*
Maximum spread spectrum range*
CLKOUT rise/fall time (20pF load)
CLKOUT logic output low (4mA load)
CLKOUT logic output high (4mA load)
FTS
FS
SS(MIN)
SS(MAX)
TRF
VOL
VOH
-0.4
*Note: After power-up, spectrum spreading of the high-frequency oscillator is disabled.
©2006 Semtech Corp.
5
Typ
5.6
21
2
±0.5
0.1
10
100
0.5
32
256
3
0.25
-0.25
Max
8
+0.3
2
60
0.4
Units
MHz
MHz
kHz
%
%
%
μs
μs
%
ppm/°C
%/sec
kHz
kHz
ns
V
Ref VDD
www.semtech.com
5 Page 
SH3003
POWER MANAGEMENT
www.DataSheet4U.com
Application Information (continued)
Low VDD Reset (continued)
On power up both the active-high and active-low reset sig-
nals are driven active. These outputs are typically valid for
a VDD level of at least 0.5V, and guaranteed to be valid for
a VDD level of 1.0V.
The reset outputs remain active until VDD rises and stays
above the level of (VBO + VHYST), where VHYST is a small
fixed amount of hysteresis, nominally 50mV, added to pre-
vent nuisance reset activations (when VDD slowly changes
near the level of VBO and some noise or power glitching is
present).
At the level of (VBO + VHYST) the power supply is consid-
ered valid. In case of the initial power-up, the reset is then
driven inactive once 6ms of valid power have elapsed. In
the case of brownout, the reset is released after a de-
lay of 6ms (but no less than 12ms from the beginning of
the brownout). Such a fast reset is possible because the
SH3003 provides a fast-starting clock that is free of crys-
tal start-up time requirements. This gives the SH3003 an
advantage over most external reset circuits, which must
have a long reset pulse duration to accommodate long
and unpredictable crystal start-up times.
The SH3003 guarantees that a valid and stable clock is
available 2ms before the reset signals are negated, so
that internal synchronous reset and initialization of the
target micro can proceed normally.
Since the clock is only active for the last 1 or 2ms of the
reset interval, when VDD has already been valid for some
time, energy savings are realized and the start-up of the
whole system is made easier. The commonly used reset
approach forces the processor to turn the oscillator on
and to run at full speed (thus consuming full power) dur-
ing the critical time when the (possibly depleted) battery is
trying to raise VDD to an acceptable level. In contrast, the
SH3003 allows the power source to charge the bypass
capacitors and raise the level of VDD with little additional
load. Only when power has stabilized is the target micro
permitted to start expending energy.
When a brownout event occurs, the SH3003 continues to
provide the clock to the target processor, but at a reduced
frequency between 500kHz and 1.0MHz. After a delay of
2ms this clock is stopped, automatically lowering the en-
ergy consumption of the whole system, (see Figure 2).
A Noise Filter (see Figure 1, Page 10) prevents reset ac-
tivations from noise and small power glitches on the VDD
line. A typical behavior is shown in Figure 3 for the VDD
level just above VBO and various amplitudes and durations
of the negative-going spikes.
When VDD is falling, both reset lines are guaranteed to
activate within 5μs from the time VBO is crossed over.
VBO + VHYST
VDD
VBO
1V
3-5 ms
RST
12 ms minimum
6 ms
NRST
Undefined
CLKOUT
1 ms
Normal
FOUT
2 ms
2 ms
Reduced FOUT
0.5-1.0 MHz
Figure 2. Operations of low VDD / Brownout Detector
10 Duration
5
Guaranteed reset
Guaranteed NO reset
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Am plitude, V
Figure 3. Response to negative voltage spikes
©2006 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH3003.PDF ] | |
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