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PDF SUD50N04-25P Data sheet ( Hoja de datos )
| Número de pieza | SUD50N04-25P | |
| Descripción | N-Channel 40-V (D-S) - 175 MOSFET | |
| Fabricantes | Vishay | |
| Logotipo |  |
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SPICE Device Model SUU/SUD50N04-25P
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N-Channel 40-V (D-S) 175°C MOSFET
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 74356
S-62520Rev. A, 18-Dec-06
www.vishay.com
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1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet SUD50N04-25P.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SUD50N04-25P | N-Channel 40-V (D-S) - 175 MOSFET | Vishay |
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