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PDF YDA146 Data sheet ( Hoja de datos )
| Número de pieza | YDA146 | |
| Descripción | Stereo 5W-30W Digital Audio Power Amplifier | |
| Fabricantes | Yamaha | |
| Logotipo |  |
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YDA146
D-530
STEREO 5W-30W DIGITAL AUDIO POWER AMPLIFIER
■Overview
YDA146 (D-530) is a high-efficiency digital audio power amplifier IC with the maximum output of 30W × 2ch.
YDA146 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate
characteristics and low noise characteristics among digital amplifier ICs in the same class.
In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use
conditions.
YDA146 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were
developed by Yamaha original digital amplifier technology.
YDA146 has overcurrent protection function for speaker output terminals, high temperature protection function, and
lowsupply voltage malfunction prevention function.
■Features
・Operating supply voltage range
PVDD: 8.0V to 16.5V
・Maximum momentary output
30 W×2ch (VDDP=15V, RL=4Ω, THD+N=10%)
20 W×2ch (VDDP=14V, RL=4Ω, THD+N=10%)
・Maximum continuous output
15 W*1×2ch
13.5W*1×2ch
(VDDP=15V, RL=8Ω, THD+N=10%, Ta=70°C)
(VDDP=15V, RL=4Ω, THD+N=10%, Ta=25°C)
・Distortion Rate (THD+N)
0.02 % (VDDP=12V, RL=8Ω, Po=0.2W, 1kHz)
・Residual Noise
48µVrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Efficiency
92 % (VDDP=12V, RL=8Ω)
・S/N Ratio
105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Channel separation
-80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・PSRR
60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
・Non-clip function/DRC function (switchable)
・Power limit function
・Clock External Synchronization Function
・Master/Slave Synchronization Function using clock outputs
・Over-current Protection Function, High Temperature Protection Function,
Low Voltage Malfunction Prevention Function, and DC Detection Function
・Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal
・Spread Clock Function
・Pop Noise Reduction Function
・Package
Lead-free 48-pin Plastic SQFP (Exposed stage)
Note) *1: A value based on Yamaha's board implementation conditions (See Note *2 of page 26)
YDA146 CATALOG
CATALOG No.:LSI-4DA146A51
2009.1
1 page  
YDA146
www.DataSheet4U.com
■Functional Description
● Digital Amplifier Function
YDA146 has digital amplifiers with analog input, PWM pulse output, the maximum output of 30W × 2ch.
Adopting “Pure Pulse Direct Speaker Drive Circuit” reduces distortion and noise on PWM pulse output signal.
・Digital Amplifier Gain
The total gain of the digital amplifier varies depending on operation modes, as shown below.
NCDRC1 NCDRC0
LL
LH
HL
HH
GAIN1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
GAIN0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Total Gain
+22dB
+28dB
+34dB
+16dB
+34dB
+40dB
+46dB
+28dB
+34dB
+40dB
+46dB
+28dB
+34dB
+40dB
+46dB
+28dB
Operation Mode
Normal mode
Non-clip: OFF
DRC: OFF
Non-clip mode
DRC1 mode
DRC2 mode
・Audio Signal Input
For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals
(Rch) through a DC-cut capacitor (CIN).
On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch)
through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut
capacitors (CIN) with the same value.
In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10kΩ or
less. Use a DC-cut capacitor (CIN) of 1µF. (The capacitance value should be less than 1.5µF throughout the operating
temperature range.)
(Cautions)
When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former
device from YDA146's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM).
For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state.
CATALOG No.:LSI-4DA146A51
5
5 Page 
YDA146
Power Lパimワit Vーaリluミeッ(トV値PL（) VPL）
VPL - 12dB
Output Voltage [dB]
www.DataSheet4U.com
A Condition パinワーwhリicミhットtがhe掛
power limit is beかingっaてpいplるied状. 態
DRC1
NCDRC[1:0]=10
OFF
NCDRC[1:0]=00
-24 Input V入olt力ag電e 圧[d[Bd]B]
Non-clip/DRC Gain Curve (DRC1)
0
Power Limit Value （VPL）
VPL - 12dB
Output Voltage [dB]
A condition in which it is not applied
even if exceeding the power limit.
DRC2
NCDRC[1:0]=11
OFF
NCDRC[1:0]=00
-24 Input Voltage [dB]
Non-clip/DRC Gain Curve (DRC2)
0
CATALOG No.:LSI-4DA146A51
11
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet YDA146.PDF ] | |
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