LC863432A 데이터시트 PDF

LC863432A 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 19 페이지수

미리보기를 사용할 수 없습니다

Ordering number : ENN*6846

CMOS IC

LC863432A/28A/24A/20A/16A

8-Bit Single-Chip Microcontroller

Preliminary

Overview

The LC863432/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks:

- CPU : Operable at a minimum bus cycle time of 0.424µs

- On-chip ROM capacity

Program ROM : 32K/28K/24K/20K/16K bytes

CGROM : 16K bytes

- On-chip RAM capacity : 512 bytes

- OSD RAM : 352 × 9 bits

- Closed-Caption TV controller and the on-screen display controller

- Closed-Caption data slicer

- Four channels × 6-bit AD Converter

- Three channels × 7-bit PWM

- 16-bit timer/counter, 14-bit base timer

- IIC-bus compliant serial interface circuit (Multi-master type)

- ROM correction function

- 11-source 8-vectored interrupt system

- Integrated system clock generator and display clock generator

Only one X’tal oscillator (32.768kHz) for PLL reference is used for both generators

TV control and the Closed Caption function

All of the above functions are fabricated on a single chip.

Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please

notify us of this in advance of our receiving your program ROM code order.

Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these

components in an IIC system, provided that the system conforms to the IIC Standard Specification as

defined by Philips.

Trademarks

IIC is a trademark of Philips Corporation.

Ver.1.01

00000

D2700 RM (IM) Shindo No.6846-1/19

LC863432A/28A/24A/20A/16A

(15) Sub-routine stack level

- A maximum of 128 levels (stack is built in the internal RAM)

(16) Multiplication/division instruction

- 16 bits × 8 bits (7 instruction cycle times)

- 16 bits / 8 bits (7 instruction cycle times)

(17) 3 oscillation circuits

- Built-in RC oscillation circuit used for the system clock

- Built-in VCO circuit used for the system clock and OSD

- X’tal oscillation circuit used for base timer, system clock and PLL reference

(18) Standby function

- HALT mode

The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is

stopped. This mode can be released by the interrupt request or the system reset.

- HOLD mode

The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be

released by the following conditions.

• Pull the reset terminal ( RES ) to low level.

• Feed the selected level to either P70/INT0 or P71/INT1.

(19) Package

- MFP36S

- DIP36S

(20) Development tools

- Flash EEPROM:

- Evaluation chip:

- Emulator:

LC86F3448A

LC863096

EVA86000 (main) + ECB863400 (evaluation chip board)

+ POD36-CABLE (cable)

+ POD36-DIP (for DIP36S)

or POD36-MFP (for MFP36S)

No.6846-4/19

Pin Description

LC863432A/28A/24A/20A/16A

Pin Description Table

Terminal

I/O

VSS -

XT1 I

XT2 O

VDD

-

RES I

FILT

O

CVIN

I

VS I

HS I

RO

GO

BO

BL O

Port 0

P00 to P07

I/O

Port 1

P10 to P17

I/O

Function Description

Negative power supply

Input terminal for crystal oscillator

Output terminal for crystal oscillator

Positive power supply

Reset terminal

Filter terminal for PLL

Video signal input terminal

Vertical synchronization signal input terminal

Horizontal synchronization signal input terminal

Red (R) output terminal of RGB image output

Green (G) output terminal of RGB image output

Blue (B) output terminal of RGB image output

Fast blanking control signal

Switch TV image signal and caption/OSD image signal

•8-bit input/output port,

Input/output can be specified in nibble unit

(If the N-ch open drain output is selected by option, the

corresponding port data can be read in output mode.)

•Other functions

AD converter input port (P04 to P07: 4 channels)

•8-bit input/output port

Input/output can be specified for each bit

(programmable pull-up resister provided)

•Other functions

P10 IIC0 data I/O

P11 IIC0 clock output

P12 IIC1 data I/O

P13 IIC1 clock output

P14 PWM1 output

P15 PWM2 output

P16 PWM3 output

Option

Pull-up resistor

provided/not provided

Output Format

CMOS/Nch-OD

Output Format

CMOS/Nch-OD

Port 3

P30 to P32

•3-bit input/output port

I/O Input/output can be specified for each bit

(CMOS output/input with programmable pull-up resister)

No.6846-7/19

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.