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PDF SC2516 Data sheet ( Hoja de datos )
| Número de pieza | SC2516 | |
| Descripción | Complete Three-in-One DDR Power Solution With BF_CUT | |
| Fabricantes | Semtech | |
| Logotipo |  |
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POWER MANAGEMENT
SC2516
Complete Three-in-One DDR
Power SolutionwwwW.DaittahSheBet4FU._coCmUT
Description
Features
The SC2516 is a fully integrated, Three-in-One DDR Con-
troller supplying power to the VDDQ, VTT and GMCH
rails. Two synchronous buck controller provide the VDDQ
and GMCH at high efficiency, while an internal linear regu-
lator supplies the termination voltage with 1.8A(min)
Source/Sink capability.
The SC2516 uses the Intel® defined Latched BF_Cut
signal to comply with motherboard state transitions. The
regulator uses the 5VDUAL rail to supply VDDQ under all
motherboard states, via the VDDQ switcher. The GMCH
regulator is slaved off the 5V main regulator, using a sepa-
rate UVLO on that rail. Additional logic and supervisory
circuitry complete the functionality of this single chip DDR
power solution in compliance with ACPI requirements.
The MLP package with a copper pad provides excellent
thermal impedance while keeping small footprint. VDDQ
short circuit protection along with VTT current limit as
well as two independent thermal shutdown circuits as-
sure safe operation under all fault conditions.
Typical Application Circuit
Uses Latched BF_Cut from Intel Glue Chip to
control regulators
External VDDQ divider allows DDRI or DDRII Com-
patibility
High efficiency VDDQ switcher
External GMCH divider allows 1.5V or 1.25V pro-
gramming
High efficiency GMCH switcher supplies pro-
grammed output from the 5V or 3.3V rail
Single chip solution complies fully with ACPI power
sequencing specifications
1.8A (min) VTT Source/Sink capability
High current 1Amp gate driver for VDDQ switcher
Independent thermal shutdown for VTT
Fast transient response
Space saving 22-pin MLP package with copper
thermal pad for heatsinking to PC Board
Applications
Power Solution for DDR memory per Intel
motherboard specification
High speed data line termination
12VCC
5Vdual
FBVDDQ
SS/EN
VTT
VDDQ
VDDQ
1 COMP
2 FBVDDQ
3
SS/EN
4 VTTGND
5 VTT
6 VDDQ
7 AGND
8 VTTFB
9 REFSENS
10 FB_GMCH
11 SS_GMCH
PGND
BG
TG
BST
5VSBY
COMP_GMCH
BF_CUT
TG_GMCH
BG_GMCH
GND_GMCH
POK
22
21
20
19
18
17
16
15
14
13
12
FB_GMCH
SC2516
ATXPWR_OK
5VSBY
Latched BF_CUT
3VCC
VDDQ
FBVDDQ
GMCH
FB_GMCH
Revision 8, May. 2005
1
www.semtech.com
1 page  
SC2516
POWER MANAGEMENT
Pin Descriptions
www.DataSheet4U.com
Pin # Pin Name
Pin Function
1 COMP Compensation pin for the PWM transconductance amplifier for the VDDQ Switcher.
2 FBVDDQ Feedback for the VDDQ regulator. Connect to the VDDQ sense at the point of load.
3 SS/EN Soft start capacitor to GND. Pull low to disable controller.
4 VTTGND VTT return. Connect to copper plane carrying VTT return current. The trace connecting to this pin
must be able to carry 2 Amps.
5 VTT VTT Regulator output. Regulates to 1/2 VDDQ. Sources or sinks 1.8 Amps. The trace connecting
to this pin must be able to carry 2 Amps.
6 VDDQ VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 Amps.
7 AGND Analog ground. Compensation components and the Soft Start Capacitor connect to this ground.
8 VTTFB Sense input for the VTT regulator. Connect to Point of Load for the VTT rail.
9 REFSNS Sense input for the VDDQ rail. VTT will be regulated to 1/2 of its voltage. Connect to Point of
Load, where the VREF for the memory is generated.
10 FB_GMCH Sense input for the GMCH. Connect to Point of Load for the GMCH rail.
11 SS_GMCH Soft start for GMCH switcher . Connect a capacitor to GND.
12 POK Connect to power OK signal from ATX power.
13 GND_GMCH Gate Drive return Ground for the GMCH regulator. Connect to Source of bottom FET.
14 BG_GMCH Bottom FET Gate drive for the GMCH regulator.
15 TG_GMCH Top FET Gate drive for the GMCH regulator.
16 BF_CUT Latched BF_CUT input from Glue Chip.
17 COMP_GMCH Compensation pin for the PWM transconductance amplifier for the GMCH Switcher
18 5VSBY Connect to 5VSTBY input.
19 BST The Top and Bottom Gate drive bus.Generated using bootstrap diode/capacitor. An additional
diode is also required to trap the peak Bootstrap voltage for the BG drive. (see typical
application circuit)
20 TG Top FET gate drive.
21 BG Bottom FET gate drive.
22 PGND Gate drive return. Keep this pin close to bottom FET source.
23 TH_PAD Copper pad on bottom of chip used for heatsinking. It must be connected to ground plane under
IC.
© 2005 Semtech Corp.
5
www.semtech.com
5 Page 
POWER MANAGEMENT
Applications Information (Cont.)
Loop Gain Mag (dB)
100
mag ( i)
50
0
50
10
phase
0
45
( i)
90
135
180
10
100
1 .10 3
1 .10 4
Fi
Loop Gain Phase (Degree)
100
1 .10 3
1 .10 4
Fi
Fig. 2. Bode plot of the VDDQ Channel
SC2516
www.DataSheet4U.com
1 .10 5
1 .10 6
1 .10 5
1 .10 6
© 2005 Semtech Corp.
Fig. 3. Bode plot of the GMCH Channel
11
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11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SC2516.PDF ] | |
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