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TSL1410R 데이터시트 PDF




TAOS에서 제조한 전자 부품 TSL1410R은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 TSL1410R 기능
기능 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
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TSL1410R 데이터시트, 핀배열, 회로
r TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
r www.DTaAOtaSS0h4e3Eet4AUP.cRoILm2007
D 1280 × 1 Sensor-Element Organization
D 400 Dot-Per-Inch (DPI) Sensor Pitch
D High Linearity and Uniformity
D Wide Dynamic Range . . . 4000:1 (72 dB)
D Output Referenced to Ground
D Low Image Lag . . . 0.5% Typ
D Operation to 8 MHz
D Single 3-V to 5-V Supply
D Rail-to-Rail Output Swing (AO)
D No External Load Resistor Required
D Replacement for TSL1410
Description
The TSL1410R linear sensor array consists of two
sections of 640 photodiodes, each with
associated charge amplifier circuitry, aligned to
form a contiguous 1280 × 1 pixel array. The device
incorporates a pixel data-hold function that
provides simultaneous-integration start and stop
times for all pixels. The pixels measure 63.5 μm by
55.5 μm with 63.5-μm center-to-center spacing
and 8-μm spacing between pixels. Operation is
simplified by internal logic that requires only a
serial-input (SI) pulse and a clock.
(TOP VIEW)
1 VPP
2 SI1
3 HOLD1
4 CLK1
5 GND
6 AO1
7 SO1
8 SI2
9 HOLD2
10 CLK2
11 SO2
12 AO2
13 VDD
The device is intended for use in a wide variety of applications including mark and code reading, OCR and
contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section)
Pixel 1
(641)
1 Integrator
S1 2 Reset
2
_1
+ S2
Sample/Hold/
Output
3
Pixel
2
(642)
Pixel
3
(643)
3, 9
Hold
Hold
Switch Control Logic
Q1 Q2
Q3
Pixel
640
(1280)
Analog
Bus
Output
Buffer
Q640 (Q1280)
Gain
Trim
13 VDD
6, 12
AO
5 GND
7, 11
SO
CLK 4, 10
2, 8
SI
640-Bit Shift Register (2 each)
The
LUMENOLOGY
r
Company
Texas
Advarnced
Optoelectronic
Solutions
Inc.
1001 Klein Road S Suite 300 S Plano, TX 75074 S (972r) 673-0759
www.taosinc.com
Copyright E 2007, TAOS Inc.
1




TSL1410R pdf, 반도체, 판매, 대치품
TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043E APRIL 2007
www.DataSheet4U.com
RElLe=ct3ri3c0alΩC, hEaer=ac1t2e.r5isμtiWcs/camt 2fc(luocnkle=s1s
MHz, VDD = 5 V, TA = 25°C, λp =
otherwise noted) (see Note 3)
640
nm,
tint
=
5
ms,
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Vout
Vdrk
PRNU
Analog output voltage (white, average over 1280 pixels)
Analog output voltage (dark, average over 1280 pixels)
Pixel response nonuniformity
See Note 4
Ee = 0
See Note 5
1.6 2 2.4 V
0 0.1 0.3 V
±20%
Nonlinearity of analog output voltage
See Note 6
±0.4%
Output noise voltage
See Note 7
1 mVrms
Re Responsivity
See Note 8
20
30
38
V/
J/cm2)
Vsat Analog output saturation voltage
SE Saturation exposure
DSNU Dark signal nonuniformity
IL Image lag
VDD = 5 V, RL = 330 Ω
VDD = 3 V, RL = 330 Ω
VDD = 5 V, See Note 9
VDD = 3 V, See Note 9
All pixels, Ee = 0, See Note 10
See Note 11
4.5 4.8
2.5 2.8
155
90
0.05
0.5%
V
nJ/cm2
0.15 V
IDD Supply current
IIH High-level input current
IIL Low-level input current
Ci Input capacitance, SI
VDD = 5 V, Ee = 0
VDD = 3 V, Ee = 0
VI = VDD
VI = 0
30 45
25 40 mA
10 μA
10 μA
25 pF
Ci Input capacitance, CLK
25 pF
NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground.
4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
8. Re(min) = [Vout(min) Vdrk(max)] ÷ (Ee × tint)
9. SE(min) = [Vsat(min) Vdrk(min)] × Ee × tint) ÷ [Vout(max) Vdrk(min)]
10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination.
11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
Vout (IL) * Vdrk
Vout (white) * Vdrk
100
Timing Requirements (see Figure 1 and Figure 2)
tsu(SI) Setup time, serial input (see Note 12)
th(SI) Hold time, serial input (see Note 12 and Note 13)
tpd(SO) Propagation delay time, SO
tw Pulse duration, clock high or low
tr, tf Input transition (rise and fall) time
tqt Pixel charge transfer time
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
13. SI must go low before the rising edge of the next clock pulse.
MIN NOM MAX UNIT
20 ns
0 ns
50 ns
50 ns
0 500 ns
20 μs
Copyright E 2007, TAOS Inc.
4
r
www.taosinc.com
The LUMENOLOGY r Company
r

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TSL1410R 전자부품, 판매, 대치품
TSL1410R
1280 × 1 LINEAR SENSOR ARRAY WITH HOLD
TYPICAL CHARACTERISTICS
www.DTaAOtaSS0h4e3Eet4AUP.cRoILm2007
SETTLING TIME
vs.
LOAD
600
VDD = 3 V
Vout = 1 V
500
470 pF
400
220 pF
300
SETTLING TIME
vs.
LOAD
600
VDD = 5 V
Vout = 1 V
500
470 pF
400
220 pF
300
200
100
00
100 pF
10 pF
200 400 600 800
RL — Load Resistance W
Figure 7
1000
200
100
00
100 pF
10 pF
200 400 600
800
RL — Load Resistance W
Figure 8
1000
APPLICATION INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13 VDD
SI1/HOLD1/HOLD2
CLK1 and CLK2
SO1
SI2
SO2
AO1/AO2
1
2 SI1/HOLD1
3
4 CLK1 and CLK2
5
6 AO1
7 SO1
8 SI2/HOLD2
9
10
11 SO2
12 AO2
13 VDD
SERIAL
PARALLEL
Figure 9. Operational Connections
The LUMENOLOGY r Company
r
www.taosinc.com
r
Copyright E 2007, TAOS Inc.
7

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TSL1410R

1280 x 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS
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