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PDF K1B6416B6C Data sheet ( Hoja de datos )
| Número de pieza | K1B6416B6C | |
| Descripción | 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory | |
| Fabricantes | Samsung semiconductor | |
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K1B6416B6C
UtRAMwww.DataSheet4U.com
Document Title
4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
Revision History
Revision No. History
0.0 Initial Draft
- Design target
Draft Date
March 11, 2004
Remark
Advance
0.1 Revised
- Deleted Deep Power Down Mode support
April 19, 2004
Advance
0.2 Revised
- Changed product code from K1B6416B7C into K1B6416B6C
May 10, 2004
Advance
0.3 Revised
- Filled out Package type(54ball FBGA 6.0mm x 8.0mm)
September 1, 2004 Preliminary
- Changed Hi-Z parameters(tCHZ, tOHZ, tBHZ, tWZ) from Max.7ns
into Max.12ns and changed tHZ from Max.10ns into Max.12ns
- Updated "Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)" in
page 23
- Added comment on standby current(ISB1) measure condition as
"Standby mode is supposed to be set up after at least one active
operation after power up. ISB1 is measured after 60ms from the time
when standby mode is set up."
- Added comment on restriction of the transition between Asynchro-
nous Write operation and Fully Synchronous bus operation(Page
10,11)
- Filled out ISB1 value, ISBP value and ICC2 value in Table 17(DC AND
OPERATING CHARACTERISTICS)
- Added Synchronous Operating Current(ICC3, Max.40mA)
- Added tCSHP(A)(CS high pulse width) parameter as Min.10ns in the
ASYNCHRONOUS AC CHARACTERISTICS
0.4 Revised
October 12, 2004 Preliminary
- Changed ISB1(< 40°C) and ISBP(3/4 block, < 40°C) from 100µA into
120µA
- Changed ISBP(1/2 block and 1/4 block, < 40°C) from 95µA into 115µA
1.0 Finalized
January 20, 2005 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 1.0
January 2005
1 page  
K1B6416B6C
UtRAMwww.DataSheet4U.com
LIST of TABLES
Table 1. Product Family
Table 2. Pin Description
Table 3. Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table
Table 4. Synchronous Burst Read & Asynchronous Write Mode Truth Table
Table 5. Synchronous Burst Read & Synchronous Burst Write Mode Truth Table
Table 6. Mode Register Setting according to Field of Function
Table 7. Mode Register Set
Table 8. MRS AC Characteristics
Table 9. Latency Count Support
Table 10. Number of Clocks for 1st Data
Table 11. Burst Sequence
Table 12. PAR Mode Characteristics
Table 13. Product List
Table 14. Absolute Maximum Ratings
Table 15. Recommended DC Operating Conditions
Table 16. Capacitance
Table 17. DC and Operating Characteristics
Table 18. Asynchronous AC Characteristics
Table 19. Asynchronous Read AC Characteristics
Table 20. Asynchronous Page Read AC Characteristics
Table 21. Asynchronous Write AC Characteristics(WE Controlled)
Table 22. Asynchronous Write AC Characteristics(UB & LB Controlled)
Table 23. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled)
Table 24. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled)
Table 25. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled)
Table 26. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled)
Table 27. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled)
Table 28. Synchronous AC Characteristics
Table 29. Burst Operation AC Characteristics
Table 30. Burst Read AC Characteristics(CS Toggling Consecutive Burst)
Table 31. Burst Read AC Characteristics(CS Low Holding Consecutive Burst)
Table 32. Burst Read AC Characteristics(Last Data Sustaining)
Table 33. Burst Write AC Characteristics(CS Toggling Consecutive Burst)
Table 34. Burst Write AC Characteristics(CS Low Holding Consecutive Burst)
Table 35. Burst Read Stop AC Characteristics
Table 36. Burst Write Stop AC Characteristics
Table 37. Burst Read Suspend AC Characteristics
Table 38. Burst Read to Asynch. Write(Address Latch Type) AC Characteristics
Table 39. Burst Read to Asynch. Write(Low ADV Type) AC Characteristics
Table 40. Asynch. Write(Address Latch Type) to Burst Read AC Characteristics
Table 41. Asynch. Write(Low ADV Type) to Burst Read AC Characteristics
Table 42. Burst Read to Burst Write AC Characteristics
Table 43. Burst Write to Burst Read AC Characteristics
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- 5 - Revision 1.0
January 2005
5 Page 
K1B6416B6C
UtRAMwww.DataSheet4U.com
MODE REGISTER SETTING OPERATION
The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Syn-
chronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode.
Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines
Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode.
Mode Register Set (MRS)
The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR),
Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applica-
tions. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes.
The mode register is written by driving CS, ADV, WE, UB, LB and MRS to VIL and driving OE to VIH during valid address. The mode
register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst
Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15
and Driver Strength uses A16~A17.
Refer to the Table below for detailed Mode Register Setting. A18~A21 addresses are "Don’t care" in Mode Register Setting.
Table 6. Mode Register Setting according to field of function
Address A17~A16 A15~A14 A13 A12 A11~A9 A8 A7~A5
Function
DS
MS
WP RFU Latency BT
BL
A4~A3
PAR
A2
PARA
A1~A0
PARS
NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type),
BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array),
PARS(Partial Array Refresh Size), RFU(Reserved for Future Use)
Table 7. Mode Register Set
Driver Strength
A17 A16
DS
00
Full Drive
01
1/2 Drive
10
1/4 Drive
A15 A14
00
01
10
Mode Select
MS*
Async. 4 Page Read / Async. Write
Sync. Burst Read / Async. Write
Sync. Burst Read / Sync. Burst Write
WAIT Polarity
RFU
A13 WP A12 RFU
0 Low Enable 0
Must
1 High Enable 1
-
Latency Count
Burst Type
Burst Length
A11 A10 A9 Latency A8 BT A7 A6 A5
BL
0 00
3 0 Linear 0 1 0
4 word
0 01
4 1 Interleave 0 1 1
8 word
0 10
5
10 0
16 word
0 11
6
1 1 1 Full(256 word)
Partial Array Refresh
PAR Array
PAR Size
A4 A3
PAR
A2
PARA
A1 A0
PARS
10
PAR Enable
0 Bottom Array 0
0 Full Array
1 1 PAR Disable 1
Top Array
0 1 3/4 Array
1 0 1/2 Array
1 1 1/4 Array
NOTE : The address bits other than those listed in the table above are reserved.
For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0.
If the reserved address bits are input, then the mode will be set into the default mode. Each field has its own default mode and
these default modes are written in blue-bold in the table above.
But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up.
A12 is a reserved bit for future use. A12 must be set as "0".
Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team.
256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.
* The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then imple-
ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode.
* The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the
transition from Synchronous burst write operation to Asynchronous write operation is prohibited.
- 11 -
Revision 1.0
January 2005
11 Page | ||
| Páginas | Total 30 Páginas | |
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