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부품번호 | A43L0632 기능 |
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기능 | 512K X 32 Bit X 2 Banks Synchronous DRAM | ||
제조업체 | AMIC Technology | ||
로고 | |||
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A43L0632
Preliminary
512K X 32 Bit X 2 Banks Synchronous DRAM
Document Title
512K X 32 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
August 1, 2005
Remark
Preliminary
PRELIMINARY (August, 2005, Version 0.0)
AMIC Technology, Corp.
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A43L0632
Pin Descriptions
Symbol
CLK
CS
CKE
A0~A10
BA
Name
Description
System Clock
Active on the positive going edge to sample all inputs.
Chip Select
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Address
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Latches row addresses on the positive going edge of the CLK with RAS low.
Row Address Strobe
Enables row access & precharge.
CAS
Column Address
Strobe
WE Write Enable
DQMi
Data Input/Output
Mask
DQ0-31
Data Input/Output
VDD/VSS
Power
Supply/Ground
VDDQ/VSSQ
Data Output
Power/Ground
NC/RFU
No Connection
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V ± 0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
PRELIMINARY (August, 2005, Version 0.0)
3
AMIC Technology, Corp.
4페이지 AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C or -40ºC to +85ºC)
Parameter
AC input levels
Input timing measurement reference level
Input rise and all time (See note3)
Output timing measurement reference level
Output load condition
Value
VIH/VIL = 2.4V/0.4V
1.4V
tr/tf = 1ns/1ns
1.4V
See Fig.2
Output
870Ω
3.3V
1200Ω
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
30pF
OUTPUT
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A43L0632
ZO=50Ω
VTT =1.4V
50Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted)
Symbol
Parameter
tCC CLK cycle time
tSAC CLK to valid
Output delay
tOH Output data hold time
tCH CLK high pulse width
tCL CLK low pulse width
tSS Input setup time
tSH Input hold time
tSLZ CLK to output in Low-Z
tSHZ CLK to output in Hi-Z
CL=CAS Latency.
CL=3
CL=2
CL=3
CL=2
CL=3
CL=2
CL=3
CL=2
CL=3
CL=2
CL=3
CL=2
-6
Min Max
-7
Min Max
Unit Note
67
1000
1000 ns 1
10 10
-5-6
ns 1,2
-6-6
2.5 - 3 - ns 2
2.5 - 3 -
ns 3
2.5 - 3 -
2.5 - 3 -
ns 3
2.5 - 3 -
1.5 - 2 -
ns 3
1.5 - 2 -
1 - 1 - ns 3
1 - 1 - ns 2
-5-6
ns
-6-6
*All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
PRELIMINARY (August, 2005, Version 0.0)
6
AMIC Technology, Corp.
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
A43L0632 | 512K X 32 Bit X 2 Banks Synchronous DRAM | AMIC Technology |
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