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PDF GTL2003 Data sheet ( Hoja de datos )
| Número de pieza | GTL2003 | |
| Descripción | 8-bit bidirectional low voltage translator | |
| Fabricantes | NXP Semiconductors | |
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GTL2003
8-bit bidirectional low voltage translator
Rev. 01 — 27 July 2007
www.DataSheet4U.com
Product data sheet
1. General description
The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide
high-speed voltage translation with low ON-state resistance and minimal propagation
delay. The GTL2003 provides 8 NMOS pass transistors (Sn and Dn) with a common gate
(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional
voltage translations between 1.0 V and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn
port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by
the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by
the pull-up resistors. This functionality allows a seamless translation between higher and
lower voltages selected by the user, without the need for directional control.
All transistors have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical, SREF and DREF can be
located on any of the other eight matched Sn/Dn transistors, allowing for easier board
layout. The translator's transistors provide excellent ESD protection to lower voltage
devices and at the same time protect less ESD-resistant devices.
2. Features
I 8-bit bidirectional low voltage translator
I Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V
buses which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels
I Provides bidirectional voltage translation with no direction pin
I Low 6.5 Ω ON-state resistance (Ron) between input and output pins (Sn/Dn)
I Supports hot insertion
I No power supply required: will not latch up
I 5 V tolerant inputs
I Low standby current
I Flow-through pinout for ease of printed-circuit board trace routing
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Packages offered: TSSOP20, DHVQFN20
1 page  
NXP Semiconductors
GTL2003www.DataSheet4U.com
8-bit bidirectional low voltage translator
8. Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to VCC). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 kΩ resistor
to a 3.3 V to 5.5 V VCC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to VCC.
1.8 V
1.5 V
1.2 V
1.0 V
VCORE
CPU I/O
200 kΩ
GTL2002
GND
SREF
S1
S2
GREF
DREF
D1
D2
5V
totem pole or
open-drain I/O
VCC
CHIPSET I/O
increase bit size
by using 8-bit GTL2003,
10-bit GTL2010,
or 22-bit GTL2000
S3 D3
S4 D4
S5 D5
Sn Dn
3.3 V
VCC
CHIPSET I/O
002aac642
Typical bidirectional voltage translation.
Fig 4. Bidirectional translation to multiple higher voltage levels such as an I2C-bus
application
GTL2003_1
Product data sheet
Rev. 01 — 27 July 2007
© NXP B.V. 2007. All rights reserved.
5 of 19
5 Page 
NXP Semiconductors
GTL2003www.DataSheet4U.com
8-bit bidirectional low voltage translator
12.2 Dynamic characteristics for CBT-type application
Table 11. Dynamic characteristics
Tamb = −40 °C to +85 °C; VGREF = 5 V ± 0.5 V; GND = 0 V; CL = 50 pF; unless otherwise specified.
Refer to Figure 10.
Symbol Parameter
Conditions
Min Typ Max Unit
tPD propagation delay
[1] - - 250 ps
[1] This parameter is warranted by the ON-state resistance, but is not production tested. The propagation delay
is based on the RC time constant of the typical ON-state resistance of the switch and a load capacitance of
50 pF, when driven by an ideal voltage source (zero output impedance).
input
output
1.5 V
tPLH
1.5 V
1.5 V
tPHL
3.0 V
0V
VOH
1.5 V
VOL
002aab664
Fig 8.
VM = 1.5 V; VI = GND to 3.0 V.
tPD is equal to the maximum of tPLH or tPHL.
Input (Sn) to output (Dn) propagation delays
GTL2003_1
Product data sheet
Rev. 01 — 27 July 2007
© NXP B.V. 2007. All rights reserved.
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet GTL2003.PDF ] | |
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