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PDF A48P3616 Data sheet ( Hoja de datos )
| Número de pieza | A48P3616 | |
| Descripción | 8M X 16 Bit DDR DRAM | |
| Fabricantes | AMIC Technology | |
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Preliminary
Document Title
8M X 16 Bit DDR DRAM
Revision History
Rev. No. History
0.0 Initial issue
www.DataSheet4U.com
A48P3616
8M X 16 Bit DDR DRAM
Issue Date
September 5, 2005
Remark
Preliminary
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
1 page  
www.DataSheet4U.com
A48P3616
Preliminary
8M X 16 Bit DDR DRAM
Input/Output Functional Description
Symbol
Type
Function
CK, CK
CKE, CKE1, CKE1
CS , CS0 , CS1
Input
Input
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK . Output
(read) data is referenced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power Down
and Self Refresh operation (all banks idle), or Active Power Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is
asynchronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during Power Down.
Input buffers, excluding CKE, are disabled during self refresh. The standard pinout includes
one CKE pin. Optional pinouts might include CKE1 on a different pin, in addition to CKE0,
to facilitate independent power down control of stacked devices.
Chip Select: All commands are masked when CS is registered high. CS provides for
external bank selection on systems with multiple banks. CS is considered part of the
command code. The standard pinout includes one CS pin. Optional pinouts might include
CS1 on a different pin, in addition to CS0 , to allow upper or lower deck selection on
stacked devices.
RAS , CAS , WE
Input
Command Inputs: RAS , CAS and WE (along with CS ) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
DM
Input
is sampled high coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading. During a Read, DM can be driven high, low, or floated.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
A0 – A11
Input
Address Inputs: Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also
provide the op-code during a Mode Register Set command.
DQ Input/Output Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data,
DQS, LDQS, UDQS Input/Output centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0- DQ7; UDQS corresponds to the data on DQ8-DQ15
NC No Connect: No internal electrical connection is present.
NU Electrical connection is present. Should not be connected at second level of assembly.
VDDQ
Supply DQ Power Supply: 2.5V ± 0.2V.
VSSQ
Supply DQ Ground
VDD
Supply Power Supply: 2.5V ± 0.2V.
VSS
Supply Ground
VREF
Supply SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
Preliminary (September 2005, Version 0.0)
4
AMIC Technology, Corp.
5 Page 
www.DataSheet4U.com
A48P3616
Preliminary
8M X 16 Bit DDR DRAM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, CK ), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below)
the DC input low (high) level.
AC Output Load Circuit Diagrams
AC Input Operating Conditions
(0 °C ≤ TA ≤ 70 °C; VDD = VDDQ = 2.5V ± 0.2V (6K/75B); VDD = VDDQ = 2.6V ± 0.1V (5T/43), See AC Characteristics)
Symbol
Parameter/Condition
Min Max Unit Note
VIH (AC)
VIL (AC)
VID (AC)
VIX (AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
VREF + 0.31
VREF – 0.31
0.62
VDDQ + 0.6
0.5*VDDQ – 0.2 0.5* VDDQ + 0.2
V
V
V
V
1, 2
1, 2
1, 2, 3
1, 2, 4
Notes:
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK .
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Preliminary (September 2005, Version 0.0)
10
AMIC Technology, Corp.
11 Page | ||
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| PDF Descargar | [ Datasheet A48P3616.PDF ] | |
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