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PDF MX25L3205A Data sheet ( Hoja de datos )
| Número de pieza | MX25L3205A | |
| Descripción | 32M-BIT [x 1] CMOS SERIAL eLiteFlash MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX25L3205Awww.DataSheet4U.com
Macronix NBitTM Memory Family
32M-BIT [x 1] CMOS SERIAL eLiteFlashTM MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 33,554,432 x 1 bit structure
• 64 Equal Sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL
Load)
- Fast program time: 3ms/page (typical, 256-byte per
page)
- Fast erase time: 1s/sector (typical, 64K-byte per
sector) and 64s/chip (typical)
- Acceleration mode:
- Program time: 2.4ms/page (typical)
- Erase time: 0.8s/sector (typical) and 51s/chip
(typical)
• Low Power Consumption
- Low active read current: 30mA (max.) at 50MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 38mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 10K erase/program cycle for array
• Minimum 100K erase/program cycle for additional 4Kb
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected
sector
- Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the
manufacturer's ID first and ADD=01H will output device
ID first
• Additional 4Kb sector independent from main memory
for parameter storage to eliminate EEPROM from
system
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO/PO7
- Serial Data Output or Parallel mode Data output/input
• WP#/ACC Pin
- Hardware write protection and Program/erase accel-
eration
• HOLD# pin
- pause the chip without disselecting the chip (not for
parallel mode, please connect HOLD# pin to VCC dur-
ing parallel mode)
• PO0~PO6
- for parallel mode data output/input
• PACKAGE
- 16-pin SOP (300mil)
- 8-land SON (8x6mm)
- All Pb-free devices are RoHS Compliant
P/N: PM1243
REV. 1.2, NOV. 06, 2006
1
1 page  
MX25L3205Awww.DataSheet4U.com
Table 1. Protected Area Sizes
Status bit
BP2 BP1
00
00
01
01
10
10
11
11
BP0
0
1
0
1
0
1
0
1
Protection Area
32Mb
None
Upper 64th (Sector 63)
Upper 32nd (two sectors: 62 and 63)
Upper sixteenth (four sectors: 60 to 63)
Upper eighth (eight sectors: 56 to 63)
Upper quarter (sixteen sectors: 48 to 63)
Upper half (thirty-two sectors: 32 to 63)
All
Note:
1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
P/N: PM1243
REV. 1.2, NOV. 06, 2006
5
5 Page 
MX25L3205Awww.DataSheet4U.com
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low-> sending RDSR instruction code-> Status Register data out
on SO (see Figure. 15)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status
register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress.
When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch.
When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write
status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase/write status register instruction.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined
in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the
Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits
define the protected area of the memory to against Page Program (PP), Sector Erase (SE), and Chip Erase(CE) instructions
(only if all Block Protect bits set to 0, the CE instruction can be executed)
Program/erase error bit. When the program/erase bit set to 1, there is an error occurred in last program/erase operation.
The Flash may accept a new program/erase command to re-do program/erase operation.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal
is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for
execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
bit 7
SRWD
Status
Register Write
Protect
1= status
register write
disable
bit 6
Program/
erase
error
1=error
bit 5 bit 4 bit 3 bit 2
bit 1
bit 0
BP2 BP1 BP0
WEL
WIP
0 the level of the level of the level of (write enable (write in progress
protected protected protected
latch)
bit)
block
block
block
(note 1) (note 1) (note 1) 1=write enable 1=write operation
0=not write 0=not in write
enable
operation
Note: 1. see the table "Protected Area Sizes"
P/N: PM1243
REV. 1.2, NOV. 06, 2006
11
11 Page | ||
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