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부품번호 | PCA9513A 기능 |
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기능 | Hot swappable I2C-bus and SMBus bus buffer | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 25 페이지수
www.DataSheet4U.com
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
Rev. 01 — 11 October 2005
Product data sheet
1. General description
The PCA9513A and PCA9514A are hot swappable I2C-bus and SMBus buffers that allow
I/O card insertion into a live backplane without corrupting the data and clock buses.
Control circuitry prevents the backplane from being connected to the card until a stop
command or bus idle occurs on the backplane without bus contention on the card. When
the connection is made, the PCA9513A and PCA9514A provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Rise time accelerator circuitry allows the use of weaker DC pull-up currents while still
meeting rise time requirements. The PCA9513A and PCA9514A incorporates a digital
ENABLE input pin, which enables the device when asserted HIGH and forces the device
into a Low current mode when asserted LOW, and an open-drain READY output pin,
which indicates that the backplane and card sides are connected together (HIGH) or not
(LOW).
The PCA9513A supplies a 92 µA current source to SCLIN and SDAIN pins in lieu of using
pull-up resistors which is ideal for multidrop bus applications. Including the current source
in the device provides for a consistent RC time constant as cards are removed and
inserted into the backplane. The current source is high-impedance whenever the pin
voltage is greater than the part VCC.
The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V to provide better
noise margin over the PCA9511A which is set to 0.6 V.
Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow
them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in
parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot
connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side
or P82B96 Sx/y side.
2. Features
s Bidirectional buffer for SDA and SCL lines increases fanout and prevents SDA and
SCL corruption during live board insertion and removal from multi-point backplane
systems
s Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards
s Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.8 V threshold)
s Rise time accelerator threshold moved from 0.6 V to 0.8 V for improved noise margin
s Active HIGH ENABLE input
s Active HIGH READY open-drain output
s High-impedance SDAn and SCLn pins for VCC = 0 V
Philips Semiconductors
PCA9513A; PCA9514Awww.DataSheet4U.com
Hot swappable I2C-bus and SMBus bus buffer
PCA9514A
SDAIN
SLEW RATE
DETECTOR
CONNECT
2 mA
BACKPLANE-TO-CARD
CONNECTION
2 mA
SLEW RATE
DETECTOR
CONNECT
VCC
SDAOUT
SCLIN
ENABLE
SLEW RATE
DETECTOR
CONNECT
0.55VCC/
0.45VCC
UVLO
100 µs
DELAY
2 mA
BACKPLANE-TO-CARD
CONNECTION
2 mA
SLEW RATE
DETECTOR
CONNECT
STOP BIT AND
BUS IDLE
0.5 µA
SCLOUT
0.55VCC/
0.45VCC
20 pF
UVLO
CONNECT
RD
QB
S
READY
GND
0.5 pF
CONNECT
Fig 2. Block diagram of PCA9514A
002aab681
PCA9513A_PCA9514A_1
Product data sheet
Rev. 01 — 11 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
4 of 25
4페이지 Philips Semiconductors
PCA9513A; PCA9514Awww.DataSheet4U.com
Hot swappable I2C-bus and SMBus bus buffer
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the VIL is above ∼0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
MASTER
buffer A
common
node
buffer B
buffer C
SLAVE B
SLAVE C
002aab581
Fig 5. System with 3 buffers connected to common node
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and buffer B
in series as shown in Figure 5. Consider if the VOL at the input of buffer A is 0.3 V and the
VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
Slave B and then from Slave B to Master. Before the direction change you would observe
VIL at the input of buffer A of 0.3 V and its output, the common node, is ∼0.4 V. The output
of buffer B and buffer C would be ∼0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is ∼0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B's output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator ∼0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ∼0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
∼0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (∼0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and buffer C
would see a false clock rather than a stretched clock, which would cause a system error.
The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V, so there is 0.2 V
more noise margin.
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The tPLH may be
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
PCA9513A_PCA9514A_1
Product data sheet
Rev. 01 — 11 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
7 of 25
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부품번호 | 상세설명 및 기능 | 제조사 |
PCA9513 | Hot swappable IC and SMBus bus buffer | Integrated Circuit Systems |
PCA9513A | Hot swappable I2C-bus and SMBus bus buffer | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |